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asix electronics corporation frist released date : jun/19/2000 2f, no.13, industry east rd. ii, science - based industrial park, hsin - chu city, taiwan, r.o.c. tel: 886 - 3 - 579 - 9500 fax: 886 - 3 - 579 - 955 8 http://www.asix.com.tw ax88790 l 3 - in - 1 pcmcia fast ethernet controller 10/100base 3 - in - 1 pcmcia fast ethernet controller document no.: ax790 - 15 / v1.5 / jan. 24 ?02 features highly integrated with embedded 10/100mbps mac, phy and transceiver compliant with ieee 802.3/802.3u 100base - tx/fx specification single chip pc mc i a bu s 10/100mbps fast ethernet mac controller embedded 8k * 16 bit sram ne2000 register level compatible instruction compliant with 16 bit pc card standard - february 1995 support both 10mbps and 100mbps data rate support both full - duplex or half - duplex opera tion provides fax/modem interface for combo ap provides an extra mii port for supporting other media. for example, home - lan application support 128 / 256 bytes eeprom (used for saving cis) support automatic loading of ethernet id, cis and adapter configurati on from eeprom on power - on initialization external and internal loop - back capability support 3 general purpose input pins low power consumption, typical under 100ma 128 - pin lqfp low profile package 0.25 micron low power cmos process. 2 5mhz operation, pure 3.3 v operation with 5v i/o tolerance . *ieee is a registered trademark of the institute of electrical and electronic engineers, inc. *all other trademarks and registered trademark are the property of their respective holders. product description the ax88 790 fast ethernet controller is a high performance and highly integrated pc mc i a bus ethernet controller with embedded 10/100mbps phy/transceiver and 8k*16 bit sram. the ax88790 contains a 16 bit pc mc i a interf ace s to host cpu and compliant with pc card stan dard ? february 1995 . the ax88790 implements both 10mbps and 100mbps ethernet function based on ieee802.3 / ieee802.3u lan standard. the ax88790 also provides an extra ieee802.3u compliant media - independent interface (mii) to support other media applicatio ns. using mii interface, home lan phy type media can be supported. the ax88790 is built in interface to connect fax/modem chipset with parallel bus interface. typical system block diagram always contact as ix for possible updates before starting a design. this data sheet contains new products information. asix electronics reserves the rights to modify product specification without notice. no liability is assumed as a result of the use of this product. no rig hts under any patent accompany the sale of the product. ax88790 with 10/100 phy/txrx modem daa magnetic rj45 rj11 pcmcia i/f eeprom home lan phy /txrx magnetic rj11
asix electronics corporation 2 ax88790 l 3 - in - 1 pcmcia fast ethernet controller contents 1.0 introduction ................................ ................................ ................................ ................................ .............. 5 1.1 g eneral d escription : ................................ ................................ ................................ ................................ ..... 5 1.2 ax88790 b lock d iagram : ................................ ................................ ................................ .............................. 5 1.3 ax8 8790 p in c onnection d iagram ................................ ................................ ................................ ............... 6 2.0 signal descripti on ................................ ................................ ................................ ................................ ... 7 2.1 pcmcia b us i nterface s ignals g roup ................................ ................................ ................................ ......... 7 2.2 eeprom s ignals g roup ................................ ................................ ................................ ................................ 8 2.3 mii inter face signals group ................................ ................................ ................................ .......................... 8 2.4 10/100m bps t wisted - p air i nterface pins group ................................ ................................ ........................... 9 2.5 b uilt - in phy led indicator pins group ................................ ................................ ................................ ....... 9 2.6 m odem interface pins group ................................ ................................ ................................ .......................... 9 2.7 g eneral p urpose i/o pins group ................................ ................................ ................................ .................. 10 2.8 m iscellaneous pins gr oup ................................ ................................ ................................ ............................ 11 2.9 p ower on configuratio n setup signals cros s reference table ................................ ................................ 12 3.0 memory and i/ o mapping ................................ ................................ ................................ ...................... 13 3.1 eeprom m emory m apping ................................ ................................ ................................ .......................... 13 3.2 a ttribute m emory m apping ................................ ................................ ................................ ........................ 13 3.3 i/o m apping ................................ ................................ ................................ ................................ ................... 14 3.4 sram m emory m apping ................................ ................................ ................................ .............................. 14 4.0 registers operat ion ................................ ................................ ................................ ............................. 15 4.1 pcmcia f unction c onfiguration r egister s et of lan ................................ ................................ ........... 15 4.1.1 configuration option register of lan (lcor) offset 3c0h (read/write) ................................ ............... 16 4.1.2 configuration and status register of lan (lcsr) offset 3c2h (read/write) ................................ ......... 17 4.1.3 i/o base register 0/1 of lan (liobase0/1) offset 3cah/3cch (read/write) ................................ ...... 17 4.2 pcmcia f unction c onfiguration r egister s et of modem ................................ ................................ .... 18 4.2.1 configuration option register of modem (mcor) offset 3e0h (read/write) ................................ ...... 18 4.2.2 configuration and status register of modem (mcsr) offset 3e2h (read/wr ite) ................................ . 19 4.2.3 i/o base register 0/1 of modem (miobase0/1) offset 3eah/3ech (read/write) .............................. 19 4.3 mac c ore r egisters ................................ ................................ ................................ ................................ .... 20 4.3.1 command register (cr) offset 00h (read/wr ite) ................................ ................................ ................... 22 4.3.2 interrupt status register (isr) offset 07h (read/write) ................................ ................................ .......... 22 4.3.3 interrupt mask register (imr) offset 0fh (write) ................................ ................................ .................... 23 4.3.4 data configuration register (dcr) offset 0eh (write) ................................ ................................ .......... 23 4.3.5 transmit configuration register (tcr) offset 0dh (write) ................................ ................................ .... 23 4.3.6 transmit status register (tsr) offset 04h (read) ................................ ................................ ................... 24 4.3.7 rece ive configuration (rcr) offset 0ch (write) ................................ ................................ .................... 24 4.3.8 receive status register (rsr) offset 0ch (read) ................................ ................................ ................... 24 4.3.9 inter - frame gap (ifg) offset 16h (read/write) ................................ ................................ ....................... 24 4.3.1 0 inter - frame gap segment 1(ifgs1) offset 12h (read/write) ................................ ................................ . 25 4.3.11 inter - frame gap segment 2(ifgs2) offset 13h (read/write) ................................ ................................ . 25 4.3.12 mii/eeprom management register (memr) offset 14h (read/wri te) ................................ ................. 25 4.3.13 test register (tr) offset 15h (write) ................................ ................................ ................................ .... 25 4.3.14 test register (tr) offset 15h (read) ................................ ................................ ................................ .... 25 4.3.15 general purpose input register (gpi) offset 17h (read) ................................ ................................ ...... 26 4.3.16 gpo and control (gpoc) offset 17h (write) ................................ ................................ ....................... 26 4.4 t he e mbedded phy r egisters ................................ ................................ ................................ ..................... 27 4.4.1 mr0 -- control register bit descriptions ................................ ................................ ................................ . 28 4.4.2 mr1 -- status register bit descriptions ................................ ................................ ................................ ... 29 4.4.3 mr2, mr3 -- identification registers (1 and 2) bit descriptions ................................ .............................. 30 4.4.4 mr4 ? autonegotiation advertisement registers bit descriptions ................................ ............................ 30 4.4.5 mr5 ? autonegotiation link partner ability (base page) register bit descriptions ................................ . 30
asix electronics corporation 3 ax88790 l 3 - in - 1 pcmcia fast ethernet controller 4.4.6 mr5 ? autonegotiation link partner (lp) ability register (next page) bit descriptions .......................... 31 4.4.7 mr6 ? autonegotiation expansion register bit descriptions ................................ ................................ ... 31 4.4.8 mr7 ? next page transmit register bit descriptions ................................ ................................ ............... 32 4.4.9 mr16 ? pcs control register bit description s ................................ ................................ ........................ 32 4.4.10 mr17 ? autonegotiation register a bit descriptions ................................ ................................ .............. 33 4.4.11 mr18 ? autonegotiation register b bit descriptions ................................ ................................ .............. 33 4.4.12 mr20 ? user defined register bit de scriptions ................................ ................................ ...................... 33 4.4.13 mr21 ? rxer counter register bit descriptions ................................ ................................ ................... 34 4.4.14 mr28 ? device - specific register 1 (status register) bit descriptions ................................ ..................... 34 4.4.15 mr29 ? device - specific register 2 (100mbps control) bit descriptions ................................ ................. 35 4.4.16 mr30 ? device - specific register 3 (10mbps control) bit descriptions ................................ ................... 36 4.4.17 mr31 ? device - specific register 4 (quick status) bit d escriptions ................................ ........................ 37 5.0 device access f unctions ................................ ................................ ................................ .................... 38 5.1 pcmcia interface access fun ctions . ................................ ................................ ................................ ......... 38 5.1.1 attribute memory access function functions. ................................ ................................ ............................ 38 5.1.1 i/o access function functions. ................................ ................................ ................................ ................... 38 5.2 mii s tation m anagement functions . ................................ ................................ ................................ ......... 39 6.0 electrical spec ification and timing s ................................ ................................ ....................... 40 6.1 a bsolute m aximum r atings ................................ ................................ ................................ ........................ 40 6.2 g eneral o peration c onditions ................................ ................................ ................................ ................... 40 6.3 dc c haracteristics ................................ ................................ ................................ ................................ ..... 40 6.4 a.c. t iming c haracteristics ................................ ................................ ................................ ....................... 41 6.4.1 xtal / clock ................................ ................................ ................................ ................................ ........ 41 6.4.2 reset timing ................................ ................................ ................................ ................................ ............ 41 6.4.3 attribute memory read timing ................................ ................................ ................................ ................ 43 6.4.4 attribute memory write timing ................................ ................................ ................................ ................ 44 6.4.5 i/o read timing ................................ ................................ ................................ ................................ ....... 45 6 .4.6 i/o write timing ................................ ................................ ................................ ................................ ...... 46 6.4.7 mii timing ................................ ................................ ................................ ................................ ............... 47 7.0 package informat ion ................................ ................................ ................................ ........................... 48 appendix a: applica tion note 1 ................................ ................................ ................................ ............. 49 a.1 u sing c rystal 25mh z ................................ ................................ ................................ ................................ . 49 a.2 u sing o scillator 25mh z ................................ ................................ ................................ ............................ 49 appendix b: power c onsumption reference data ................................ ................................ ...... 50 errata of ax88790 ................................ ................................ ................................ ................................ .......... 51 demonstration circui t (a) : ax88790 + homepna 1m8 phy ................................ .......................... 52 demonstration circui t (b) : ax88790 onl y ................................ ................................ ....................... 57
asix electronics corporation 4 ax88790 l 3 - in - 1 pcmcia fast ethernet controller figures f ig - 1 ax88790 b lock d iagram ................................ ................................ ................................ ............................. 5 f ig - 2 ax88790 p in c onnection d iag ram ................................ ................................ ................................ .............. 6 tables t ab - 1 pcmcia bus interface signal s group ................................ ................................ ................................ ........ 7 t ab - 2 eeprom bus interface signal s group ................................ ................................ ................................ ....... 8 t ab - 3 mii interface signals gr oup ................................ ................................ ................................ ....................... 8 t ab - 4 10/100m bps t wisted - p air i nterface pins group ................................ ................................ ......................... 9 t ab - 5 b uilt - in phy led indicator pins group ................................ ................................ ................................ .... 9 t ab - 6 m odem interface signa ls group ................................ ................................ ................................ ............... 10 t ab ? 7 g eneral p urposes i/o pins group ................................ ................................ ................................ ............. 1 0 t ab ? 8 m iscellaneous pins gr oup ................................ ................................ ................................ ........................ 11 t ab - 9 p ower on c onfiguration s etup t able ................................ ................................ ................................ ..... 12 t ab ? 10 eeprom m emory m apping ................................ ................................ ................................ .................... 13 t ab ? 11 a ttribute m emory m apping ................................ ................................ ................................ ................... 13 t ab ? 12 i/o a ddress m apping ................................ ................................ ................................ ............................... 14 t ab ? 13 l ocal m emory m apping ................................ ................................ ................................ .......................... 14 t ab ? 14 pcmcia f unction c onfigurat ion r egister m apping of lan ................................ ............................. 15 t ab ? 15 pcmcia f unction c onfiguration r egister m apping of modem ................................ ...................... 18 t ab - 16 p age 0 of mac c ore r egisters m apping ................................ ................................ ................................ 20 t ab - 17 p age 1 of mac c ore r egisters m apping ................................ ................................ ................................ 21 t ab ? 18 t he e mbedded phy r egisters ................................ ................................ ................................ ................ 27 t ab - 19 mii m anagement f rame f ormat ................................ ................................ ................................ ............ 39 t ab - 20 mii m anagement f rames - field d escription ................................ ................................ ......................... 39
asix electronics corporation 5 ax88790 l 3 - in - 1 pcmcia fast ethernet controller 1.0 introduction 1.1 general description: the ax88790 provides industrial standard ne2000 registers level compatible instruction set. various drivers are easy acquired, maintenance and usage with no pain and tears the ax887 90 fast ethernet controller is a high performance and highly integrated pc mc i a bus ethernet controller with embedded 10/100mbps phy/transceiver and 8k*16 bit sram. the ax88790 contains a 16 bit pc mc i a interf ace s to host cpu and compliant with pc card stand ard ? february 1995 . the ax88790 implements both 10mbps and 100mbps ethernet function based on ieee802.3 / ieee802.3u lan standard. the ax88790 also provides an extra ieee802.3u compliant media - independent interface (mii) to support other media application s. using mii interface, home lan phy type media can be supported. the ax88790 is also built in interface to connect fax/modem chipset with parallel bus interface. the main difference between ax88790 and ax88190 are: 1) embedded packet buffer memory 2) bui lt - in 10/100mbps phy/transceiver 3) replace memory i/f with phy/transceiver i/f. 4) fix oe# signal synchronous problem 5) fix interrupt status can?t always clean up problem of ax88190. 6) add 3 general - purpose input pins. ax88790 use 128 - pin lqfp low prof ile package, 2 5mhz o peration, and single 3.3v operation with 5v i/o tolerance . the ultra low power consumption is an outstanding feature and enlarges the application field. it is suitable for some power consumption sensitive product like compact flash adap ter card, pda (personal digital assistant) and palm size computer ?etc. 1.2 ax88790 block diagram: fig - 1 ax88790 block diagram mac core & phy 8k* 16 sram and memory arbiter remote dma fifos ne2000/gpi registers pcmcia interface sta seeprom loader i/f sd[15:0 ] sa[9:0] ctl bus mii i/f smdc smdio eecs eeck eedi eedo modem i/f tpi, tpo gpi
asix electronics corporation 6 ax88790 l 3 - in - 1 pcmcia fast ethernet controller 1.3 ax88790 pin connection diagram the a x88790 is housed in the 128 - pin plastic light quad flat pack. see fig - 2 ax88790 pin connection diagram . fig - 2 ax88790 pin connection diagram mpwdn i_act vdd sa[1] mreset# vss mint vss mrdy lclk/xtalin vdd vss vss vdd maudio mdcs# vdd mrin# vss iois16# vss tpin tpip vsso tpon tpop vsso vdda rext100 rext10 i_link i_speed gpi[0]/link sd[0] sd[1] sd[2] sd[3] sa[0] sa[3] sa[2] sa[5] sa[4] sa[6] sa[7] sa[9] sa[8] ireq# we# iord# iowr# oe# sd[15] sd[14] sd[13] sd[12] sd[11] sd[10] sd[9] sd[8] sd[6] sd[4] sd[5] sd[7] wait# reset inpack# ce2# ce1# xtalout eedi eedo eeck eecs stschg# spkr# reg# vdd vdd vss vss vssa vssa clko25m fast_mode# test1 eeprom_size mdc mdio tx_en tx_clk rxd[3] rxd[2] rxd[1] rxd[0] rx_clk crs col rx_dv txd[0] txd[1] txd[2] txd[3] gpi[1]/dpx gpi[2]/spd rextbs 123 118 122 78 70 64 54 41 32 24 12 8 117 75 57 42 26 31 21 107 105 66 65 63 60 25 16 13 3 7 128 115 112 61 33 111 43 19 15 4 109 106 77 62 11 6 71 49 17 68 58 56 55 45 23 53 116 113 59 36 34 1 124 108 28 22 9 126 119 110 121 79 74 80 72 46 29 52 10 67 44 39 27 51 5 127 125 120 114 73 69 38 48 76 47 35 30 20 2 40 37 50 18 14 ax88790 103 104 82 91 81 86 93 94 84 87 95 96 90 88 92 85 89 83 98 97 99 100 102 101 vdda vsspd vddpd vddm vssm vssa vdda vssa vssa vss vdda vss vdd vdd vss test2 iddq bist vsso vddo vssm zvreg vss
asix electronics corporation 7 ax88790 l 3 - in - 1 pcmcia fast ethernet controller 2.0 signal description the following terms describe the ax88790 pin - out: all pin names with the ?#? suffix are asserted low. the following abbreviations are used in following tables . i input pu pull up o output pd pull down i/o input/output p powe r pin od open drain 2.1 pcmcia bus i nterface s ignals g roup signal type pin no. description sa [9:0] i/pd 15, 12 ? 4 system address: signals sa[9:0] are address bus input lines which enable direct address of up to 2k memory and i/o spaces on card. s d[15:0] i/o /pd 23 ? 26, 29 ? 33, 35 ? 39, 41 ? 42 system data bus: signals sd[15:0] constitute the bi - directional data bus. ireq# o 16 interrupt request: ireq# is asserted to indicate the host system that the pc card device requires host software service . wait# o 2 wait: this signal is set low to insert wait states during remote dma transfer. reg# i /pu 128 attribute memory and i/o space select: when the reg# signal is asserted, access is limited to attribute memory and to the i/o space. iord# i /pu 19 i /o read: the host asserts iord# to read data from ax88790 i/o space. iowr# i /pu 18 i/o write: the host asserts iowr# to write data into ax88790 i/o space. oe# i /pu 20 output enable : the oe# line is used to gate memory read data from memory on pc card w e# i /pu 17 write enable: the we# signal is used for strobing memory write data into the memory on pc card. iois16# o 123 i/o is 16 bit port: the iois16# is asserted when the address at the socket corresponds to an i/o address to which the card responds, a nd the i/o port addressed is capable of 16 - bit access. inpack# o 1 input port acknowledge: the signal is asserted when the ax88790 is selected and can respond to and i/o read cycle at the address on the address bus. ce1 # - ce2 # i /pu 22, 21 card enable : th e ce1# enables even numbered address bytes and ce2# enables odd numbered address bytes stschg# o 124 battery voltage detect 1 / status change spkr# o 125 battery voltage detect 2 / audio speaker out tab - 1 pcmcia b us interface s ignals group
asix electronics corporation 8 ax88790 l 3 - in - 1 pcmcia fast ethernet controller 2.2 eeprom s ignals g roup signal type pin no. description eecs o 51 eeprom chip select: eeprom chip select signal. eeck o /pd 50 eeprom clock: signal connected to eeprom clock pin. eedi o 49 eeprom data in: signal connected to eeprom data input pin. eedo i /pu 48 eeprom data out: signal connected to eeprom data output pin. tab - 2 eeprom bus interface signals group 2.3 mii interface signals group signal type pin no. description rxd[3:0] i/pu 98 ? 95 receive da ta: rxd[3:0] is driven by the phy synchronously with respect to rx_clk. crs i/pd 100 carrier sense: asynchronous signal crs is asserted by the phy when either transmit or receive medium is non - idle. rx_dv i/pd 102 receive data valid: rx_dv is driven by t he phy synchronously with respect to rx_clk. asserted high when valid data is present on rxd [3:0]. rx_er (omit) no support receive error: rx_er is driven by phy and synchronous to rx_clk, is asserted for one or more rx_clk periods to indicate to the por t that an error has detected. rx_clk i/pu 99 receive clock: rx_clk is a continuous clock that provides the timing reference for the transfer of the rx_dv, rxd[3:0] and rx_er signals from the phy to the mii port. col i /pd 101 collision: this signal is dr iven by phy when collision is detected. tx_en o 108 transmit enable: tx_en is transition synchronously with respect to the rising edge of tx_clk. tx_en indicates that the port is presenting nibbles on txd [3:0] for transmission. txd[3:0] o 112 ? 109 tran smit data: txd[3:0] is transition synchronously with respect to the rising edge of tx_clk. for each tx_clk period in which tx_en is asserted, txd[3:0] are accepted for transmission by the phy. tx_clk i /pu 107 transmit clock: tx_clk is a continuous clock f rom phy. it provides the timing reference for the transfer of the tx_en and txd[3:0] signals from the mii port to the phy. mdc o/pu 67 station management data clock: the timing reference for mdio. all data transfers on mdio are synchronized to the rising edge of this clock. mdc is a 2.5mhz frequency clock output. mdio i/o/pu 66 station management data input / output: serial data input/output transfers from/to the phys. the transfer protocol conforms to the ieee 802.3u mii specification. tab - 3 mii interface signals group
asix electronics corporation 9 ax88790 l 3 - in - 1 pcmcia fast ethernet controller 2.4 10/100mbps twisted - pair interface pins group signal type pin no. description received data. positive differential received 125m baud mlt3 or 10m baud manchester data from magnetic . tpip i 70 fiber - opt ic data input. positive differential received 125m baud pseudo - ecl data from fiber transceiver. received data. negative differential received 125m baud mlt3 or 10m baud manchester data from magnetic . tpin i 71 fiber - optic data input. negative differen tial received 125m baud pseudo - ecl data from fiber transceiver. transmit data. positive differential transmit 125m baud mlt3 or 10m baud manchester data to magnetic . tpop o 88 fiber - optic data output. positive differential transmit 125m baud pseudo - ec l compatible data to fiber transceiver. transmit data. negative differential transmit 125m baud mlt3 or 10m baud manchester data to magnetic . tpon o 87 fiber - optic data output. negative differential transmit 125m baud pseudo - ecl compatible data to fib er transceiver. rext10 i 84 current setting 10mbits/s. an external resistor 20.1 k ohm is placed from this signal to ground to set the 10mbits/s tp driver transmit output level. rext100 i 83 current setting 10 0 mbits/s. an external resistor 2.49 k ohm is pl aced from this signal to ground to set the 100mbits/s tp driver transmit output level. rextbs i 74 external bias resistor. band gap reference for the receive channel. connect this signal to a 24.9 k ohm +/ - 1 percent resistor to ground. the parasitic load capacitance should be less than 15 pf. tab - 4 10/100mbps twisted - pair interface pins group 2.5 built - in phy led indicator pins group signal type pin no. description i_act or i_full/col o 62 active status: when i_op is logi c 1. if there is activity, transmit or receive, on the line occurred , the output will be driven low for 0.67 sec and then driven high at least 0.67 sec. full - duplex /collision status. when i_op is logic 0. if this signal is low , it indicates full - duplex lin k established , and if it is high , then the link is in half - duplex mode . when in half - duplex and c ollision occurrence , the output will be driven low for 0.67 sec and driven high at least 0.67 sec. i_speed o 61 speed status: if this signal is low , it indica tes 100mbps , and if it is high , then the speed is 10mbps . i_link or i_lk/act o 60 link status: when i_op is logic 1. if this signal is low , it indicates link, and if it is high , then the link is fail . link status /active: when i_op is logic 0. if this sig nal is low , it indicates link, and if it is high , then the link is fail . when in link status and line activity occurrence , the output will be driven low for 0.67 sec and driven high at least 0.67 sec. tab - 5 built - in phy led indic ator pins group 2.6 modem interface pins group
asix electronics corporation 10 ax88790 l 3 - in - 1 pcmcia fast ethernet controller signal name type pin no. description mrdy i/pu 122 modem ready: mrdy low indicates that modem is initializing the modem after reset signal asserted or the modem is at sleep/stop mode. mreset # o 121 modem r eset: this signal asserts low to reset the modem chipset. mdcs # o/pu 116 modem chip select: this signal connected to modem chip select pin. mpwdn o/pu 120 modem power down: rockwell modem chipset, this signal asserts low to let modem chipset into power d own mode. at&t modem chipset, this signal asserts high to let modem chipset into power down mode. mint i/pd 117 modem interrupt: this signal driven by modem chipset to active interrup t . mrin# i/pu 119 ring input: this signal is driven by daa ? s ring dete ct circuit. when a telephone - ringing signal is being received. maudio i/pu 118 modem audio: this signal is passed to pcmcia interface via spkr. tab - 6 modem interface signals group 2.7 general purpose i/o pins group signal name type pin no. description gpi[2]/spd i/pu 113 read register offset 17h bit 6 value reflects this input value. gpi[1]/dpx i/pu 106 read register offset 17h bit 5 value reflects this input value. gpi[0]/link i/pu 103 read register offset 17h bit 4 value r eflects this input value. tab ? 7 general purposes i/o pins group
asix electronics corporation 11 ax88790 l 3 - in - 1 pcmcia fast ethernet controller 2.8 miscellaneous pins group signal type pin no. description lclk/xtalin i 79 cmos local clock: typical a 25mhz clock, +/ - 100 ppm, 40% - 60% duty cycle. the signa l not supports 5 volts tolerance ( see application note also ) crystal oscillator input: typical a 25mhz crystal, +/ - 25 ppm can be connected across xtalin and xtalout. xtalout o 80 crystal oscillator output: typical a 25mhz crystal, +/ - 25 ppm can be con nected across xtalin and xtalout. if a single - ended external clock (lclk) is connected to xtalin, the crystal output pin should be left floating. clko25m o 44 clock output: this clock is source from lclk/xtalin. reset i /pu 3 reset reset is active high th en place ax88790 into reset mode immediately. during falling edge the ax88790 loads the power on setting data. and, after the falling edge the ax88790 loads the eeprom data. test[2:1] i/pd 47, 65 test pins : active high these pins are just for test mode s etting purpose only. must be pull down or keep no connection when normal operation. iddq i 46 for test only. must be pulled down at normal operation. bist i/pd 45 for test only. must be pulled down or keep no connection when normal operation. fast_mode# i/pu 59 fast_mode : active low the pin is just for test mode only. must be pulled high or keep no connection when normal operation. eeprom_size i/pu 58 eeprom size = 0: 93c46 type 128 byte eeprom is used. eeprom size = 1: 93c56 type 256 byte eeprom is us ed. zvreg o 92 this sets the common mode voltage for 10base - t and 100base - tx modes. it should be connected to the center tap of the transmit side of the transformer vdd p 13, 27, 40, 53, 57, 104, 114, 126 power supply: +3.3v dc. vss p 14, 28, 34, 43, 5 2, 54, 63, 64, 94, 105,115, 127 power supply: +0v dc or ground. vdda p 56, 69, 73, 82 power supply for analog circuit: +3.3v dc. vssa p 55, 68, 72, 75, 85, power supply for analog circuit: +0v dc or ground. vddm p 76 powers the analog block around the transmit/receive area. this should be connected to vdda: +3.3v dc. vssm p 77, 93 powers the analog block around the transmit/receive area. this should be connected to vssa: +0v dc or ground power. vddpd p 78 the phase detector (or pll) power. this should be isolated with other power: +3.3v dc. vsspd p 81 the phase detector (or pll) power. this should be isolated with other power: +0v dc or ground. vddo p 91 power supply for transceiver output driver: +3.3v dc. vsso p 86, 89, 90 power supply for transce iver output driver: +0v dc or ground. tab ? 8 miscel laneous pins group
asix electronics corporation 12 ax88790 l 3 - in - 1 pcmcia fast ethernet controller 2.9 power on configuration setup signals cross reference table signal name share with description mpd_set mpwdn mpd_set = 0: mpwdn pin active high. mpd_set = 1: mpwdn pin active low. (default) ppd_set eeck ppd_set = 0: internal phy in normal mode. (default) ppd_set = 1: internal phy in power down mode. i_op mdcs# led indicator option: selection of led display mode. i_op = 0: i_lk/act, i_speed and i_full/co l led display mode. i_op = 1: i_link, i_speed and i_act led display mode. (default) tab - 9 power on configuration setup table
asix electronics corporation 13 ax88790 l 3 - in - 1 pcmcia fast ethernet controller 3.0 memory and i/o mapping there are four memories or i/o mapping used in ax88790. 1. eeprom memory mapping 2. attribute memory mapping 3. i/o mapping 4. local memory mapping 3.1 eeprom memory mapping eeprom offset high byte low byte 00h reserved word count 01h cfh cfl 02h node - id1 node id 0 03h node id 3 node id 2 04h node id 5 node id 4 05h checksum r eserved 06h ? 10h reserved reserved 10h ? ffh cis cis tab ? 10 eeprom memory mapping note: bit 3 register of lcor in ax88190 is replaced by bit 0 of cfl in ax88790 bit 0 of cfl: enable power down mode this bit is set to 1; the lan will go into power down mode. at power down mode ax88790 will disable mac transmitting and receiving operation. but the host interface will not be affected. 3.2 attribute memory mapping attribute memory offset contents 00 00 h 03bfh cis 03c0h lcor 03 c2h lccsr 03c4h - 03c6h - 03cah liobase0 03cch liobase1 03ceh 03dfh reserved 03e0h mcor 03e2h mccsr 03e4h - 03e6h - 03eah miobase0 03ech miobase1 03eeh 03ffh reserved tab ? 11 attribute memory mapping
asix electronics corporation 14 ax88790 l 3 - in - 1 pcmcia fast ethernet controller 3.3 i/o mapping system i/o offset function 00 00 h 001fh mac core register tab ? 12 i/o address mapping 3.4 sram memory mapping offset function 00 00 h 03bfh cis *1 03c0h l cor *1 03c2h l ccsr *1 03c4h - 03c6h - 03cah l iobase0 *1 03cch l i obase1 *1 03ceh 03dfh reserved 03e0h mcor *1 03e2h mccsr *1 03e4h - 03e6h - 03eah miobase0 *1 03ech miobase1 *1 03eeh 03ffh reserved 0400h node id 0 0401h node id 1 0402h node id 2 0403h node id 3 0404h node id 4 0405h node id 5 0406h 07ff h reserved 40 00h 7 fffh 8k x 16 sram buffer tab ? 13 local memory mapping
asix electronics corporation 15 ax88790 l 3 - in - 1 pcmcia fast ethernet controller 4.0 registers operation the re are four register sets in ax88790: the pcmcia function configuration registers of lan . the pcmcia function configuratio n registers of modem . t he mac core register . t he embedded phy register s . 4.1 pcmcia function configuration register set of lan register name offset lcor configuration option register 3c 0h l csr configuration and st atus register 3c2h l iobase0 i/o based register 0 3cah l iobase1 i/o based register 1 3cch tab ? 14 pcmcia function configuration register mapping of lan
asix electronics corporation 16 ax88790 l 3 - in - 1 pcmcia fast ethernet controller 4.1.1 configuration option register of lan (lcor) offset 3c0h (read/write) field r/w/c description 7 r/w soft ware reset assert this bit will reset the lan function of ax88790 . return a 0 to this bit will leave the lan function of ax88790 in a post - reset state as same as that following hardware reset. the value of this bit is 0 at power - on. 6 r/w level irq this bit should be set to 1 ; the ax88790 always generates level mode interrupt. 5:0 r/w function configuration index these six bits are used to indicate entry of the card configuration table locate in the cis. the default value is 0 . on multifunction pc car d, bit 5, bit 4, bit 3 : modem i/o base registers bit 5 bit 4 bit 3 lan i/o base modem i/o base 0 0 0 300h decided by miobase registers 0 0 1 320h 2f8h 0 1 0 340h 3e8h 0 1 1 360h 2e8h 1 0 0 380h decided by miobase registers 1 0 1 200h 2f8h 1 1 0 220h 3e8h 1 1 1 240h 2e8h bit 2 : enable ireq# routing if bit 0 of lcor is set to 0, this bit is ignored. if bit 0 of lcor is set to 1 and this bit is set to 1, the lan will generate interrupt request via ireq# signal. if t his bit is set to 0, the lan will not generate interrupt request via ireq# line. bit 1 : enable base and limit registers if bit 0 of lcor is set to 0, this bit is ignored. if bit 0 of lcor is set to 1 and this bit is set to 1,only i/o addresses that ar e qualified by the base and limit registers are passed to lan function. if this bit is set to 0,all i/o addresses are passed to lan function. bit 0 : enable function if this bit is set to 0, the lan function is disabled. if this bit is set to 1, the la n function is enabled.
asix electronics corporation 17 ax88790 l 3 - in - 1 pcmcia fast ethernet controller 4.1.2 configuration and status register of lan (l cs r) offset 3c2h (read/write) field r/w/c description 7:3 - reserved 2 r/w ppwrdwn : phy power down setting while this bit set to 1, ax88790 will force embedded phy into power down mode. as for ppwdn is active high or active low. please refer section 2.9 power on configuration setup signal cross - reference table. note: the master control of power down mode is place on bit 0 of cfl. if user want to enable power down mode, must set the relative bit of eeprom that map to bit 0 of cfl register to logic 1. when this bit is set to 1, the lan will go into power down mode. at power down mode ax88790 will disable mac transmitting and receiving operation. but the host interface will not be affected. 1 r intr: interrupt request the lan function will set this bit to 1 when it need interrupt service and set it to 0 when it is not request interrupt service. 0 r intrack: interrupt acknowledge this bit will be 0. the intr will reflect the status of interrupt requesting. 4.1.3 i/o base register 0/1 of lan (liobase0/1) offset 3cah/3cch (read/write) the i/o base registers (liobase0 and liobase1) determine the base address of the i/o range used to access the lan specific registers (mac core regi sters). i/o base register 0 field r/w/c description 7:0 r/w base i/o address bit 7 ? 0. i/o base register 1 field r/w/c description 7:0 r/w base i/o address bit 15 ? 8.
asix electronics corporation 18 ax88790 l 3 - in - 1 pcmcia fast ethernet controller 4.2 pcmcia function configuration register set of modem register name offset mcor configuration option register 3e 0h m csr configuration and st atus register 3e2h m iobase0 i/o based register 0 3eah m iobase1 i/o based register 1 3ech tab ? 15 pcmcia function configuration register mapping of modem 4.2.1 configuration option register of modem (mcor) offset 3e0h (read/write) field r/w/c description 7 r/w software reset assert this bit will reset the modem function of ax88790 . return a 0 to this bit will leave the modem function of ax88790 in a p ost - reset state as same as that following hardware reset. the value of this bit is 0 at power - on. 6 r/w level irq this bit should be set to 1 ; the ax88790 always generates level mode interrupt. 5:0 r/w function configuration index these six bits are u sed to indicate entry of the card configuration table locate in the cis. the default value is 0 . on multifunction pc card, bit 5, bit4 : reserved bit 3 : mint route to stschg# if bit 0 of mcor is set to 0, this bit is ignored. if both bit 0 and bi t 2 of mcor are set to 1 and this bit is set to 1, the modem will route interrupt request to stschg# signal. if this bit is set to 0, the modem will generate interrupt request via ireq# line. bit 2 : mint route to ireq# (enable ireq# routing) if bit 0 of mcor is set to 0, this bit is ignored. if bit 0 of mcor is set to 1 and this bit is set to 1, the modem will generate interrupt request via ireq# signal. if this bit is set to 0, the modem will not generate interrupt request via ireq# line. bit 1 : enable base and limit registers if bit 0 of mcor is set to 0, this bit is ignored. if bit 0 of mcor is set to 1 and this bit is set to 1,only i/o addresses that are qualified by the base and limit registers are passed to modem function. if this bit is set to 0,all i/o addresses are passed to lan function. bit 0 : enable function if this bit is set to 0, the modem function is disabled. if this bit is set to 1, the modem function is enabled.
asix electronics corporation 19 ax88790 l 3 - in - 1 pcmcia fast ethernet controller 4.2.2 configuration and status register of modem (m cs r) of fset 3e2h (read/write) field r/w/c description 7:3 - reserved 2 r/w mpwrdwn : modem power down setting while this bit set to 1, mpwdn pin (pin 116) will be active to force modem chip into power down mode. as for mpwdn is active high or active low. pleas e refer section 2.7 power on configuration setup signal cross - reference table. 1 r intr: interrupt request the lan function will set this bit to 1 when it need interrupt service and set it to 0 when it is not request interrupt service. 0 r intrack: inter rupt acknowledge this bit will be 0. the intr will reflect the status of interrupt requesting. 4.2.3 i/o base register 0/1 of modem (miobase0/1) offset 3eah/3ech (read/write) the i/o base registers (miobase0 and miobase1) determine the base address of the i/o range used to access the modem specific registers. i/o base register 0 field r/w/c description 7:0 r/w base i/o address bit 7 ? 0. i/o base register 1 field r/w/c description 7:0 r/w base i/o address bit 15 ? 8.
asix electronics corporation 20 ax88790 l 3 - in - 1 pcmcia fast ethernet controller 4.3 mac core regis ters all registers of mac core are 8 - bit wide and mapped into pages which are selected by ps (page select) in the command register. page 0 (ps 1 =0 ,ps0=0 ) offset read write 00h command register ( cr ) command register ( cr ) 01h page start register ( ps tart ) page start register ( pstart ) 02h page stop register ( pstop ) page stop register ( pstop ) 03h boundary pointer ( bnry ) boundary pointer ( bnry ) 04h transmit status register ( tsr ) transmit page start address ( tpsr ) 05h number of collisi ons register ( ncr ) transmit byte count register 0 ( tbcr0 ) 06h current page register ( cpr ) transmit byte count register 1 ( tbcr1 ) 07h interrupt status register ( isr ) interrupt status register ( isr ) 08h current remote dma address 0 ( crda0 ) r emote start address register 0 ( rsar0 ) 09h current remote dma address 1 ( crda1 ) remote start address register 1 ( rsar1 ) 0ah reserved remote byte count 0 ( rbcr0 ) 0bh reserved remote byte count 1 ( rbcr1 0 0ch receive status register ( rsr ) rece ive configuration register ( rcr ) 0dh frame alignment errors ( cntr0 ) transmit configuration register ( tcr ) 0eh crc errors ( cntr1 ) data configuration register ( dcr ) 0fh missed packet errors ( cntr2 ) interrupt mask register ( imr ) 10h 11h da ta port data port 12h ifgs1 ifgs1 13h ifgs2 ifgs2 14h mii/eeprom access mii/eeprom access 15h test register test register 16h inter - frame gap ( ifg ) inter - frame gap ( ifg ) 17h gpi gpoc 18h - 1eh reserved reserved 1fh reset reserved tab - 16 page 0 of mac core registers mapping
asix electronics corporation 21 ax88790 l 3 - in - 1 pcmcia fast ethernet controller page 1 ( ps1=0, ps 0 =1) offset read write 00h command register ( cr ) command register ( cr ) 01h physical address register 0 ( para0 ) physical address register 0 ( par0 ) 02h physical address register 1 ( para1 ) physical address register 1 ( par1 ) 03h physical address register 2 ( para2 ) physical address register 2 ( par2 ) 04h physical address register 3 ( para3 ) physical address register 3 ( par3 ) 05h physical address register 4 ( para4 ) physical address register 4 ( par4 ) 06h physical address register 5 ( para5 ) physical address register 5 ( par5 ) 07h current page register ( cpr ) current page register ( cpr ) 08h multicast address register 0 ( mar0 ) multicast addres s register 0 ( mar0 ) 09h multicast address register 1 ( mar1 ) multicast address register 1 ( mar1 ) 0ah multicast address register 2 ( mar2 ) multicast address register 2 ( mar2 ) 0bh multicast address register 3 ( mar3 ) multicast address register 3 ( mar3 ) 0ch multicast address register 4 ( mar4 ) multicast address register 4 ( mar4 ) 0dh multicast address register 5 ( mar5 ) multicast address register 5 ( mar5 ) 0eh multicast address register 6 ( mar6 ) multicast address register 6 ( mar6 ) 0fh multicast address register 7 ( mar7 ) multicast address register 7 ( mar7 ) 10h 11h data port data port 12h inter - frame gap segment 1 ifgs1 inter - frame gap segment 1 ifgs1 13h inter - frame gap segment 2 ifgs2 inter - frame gap segment 2 ifgs2 14h mii/eeprom access mii/eeprom access 15h test register test register 16h inter - frame gap ( ifg ) inter - frame gap ( ifg ) 17h gpi gpoc 18h - 1eh reserved reserved 1fh reset reserved tab - 17 page 1 of mac core registers mapping
asix electronics corporation 22 ax88790 l 3 - in - 1 pcmcia fast ethernet controller 4.3.1 command register (cr) offset 00h (read/write) field name description 7 :6 ps 1,ps0 ps 1,ps0 : page select the two bits selects which register page is to be accessed. ps1 ps0 0 0 page 0 0 1 pa ge 1 5:3 rd2,rd1 ,rd0 rd2,rd1,rd0 : remote dma command these three encoded bits control operation of the remote dma channel. rd2 could be set to abort any remote dma command in process. rd2 is reset by ax88790 when a remote dma has been completed. the remo te byte count should be cleared when a remote dma has been aborted. the remote start address is not restored to the starting address if the remote dma is aborted. rd2 rd1 rd0 0 0 0 not allowed 0 0 1 remote read 0 1 0 remote write 0 1 1 not allowed 1 x x abort / complete remote dma 2 txp txp : transmit packet this bit could be set t o initiate transmission of a packet 1 start start : this bit is used to active ax88790 operation. 0 stop stop : stop ax88790 this bit is used to stop the ax88790 operation. 4.3.2 interrupt status register (isr) offset 07h (read/write) field name des cription 7 rst reset status : set when ax88790 enters reset state and cleared when a start command is issued to the cr. writing to this bit is no effect. 6 rdc remote dma complete set when remote dma operation has been completed 5 cnt counter overf low set when msb of one or more of the tally counters has been set. 4 ovw over write: set when receive buffer ring storage resources have been exhausted. 3 txe transmit error set when packet transmitted with one or more of the following errors n exces sive collisions n fifo under - run 2 rxe receive error indicates that a packet was received with one or more of the following errors crc error frame alignment error fifo overrun missed packet 1 ptx packet transmitted ind icates packet transmitted with no error 0 prx packet received indicates packet received with no error.
asix electronics corporation 23 ax88790 l 3 - in - 1 pcmcia fast ethernet controller 4.3.3 interrupt mask register (imr) offset 0fh (write) field name description 7 - reserved 6 rdce dma complete interrupt enable. default ?low? disabled. 5 cnte counter overflow interrupt enable. default ?low? disabled. 4 ovwe overwrite interrupt enable. default ?low? disabled. 3 txee transmit error interrupt enable. default ?low? disabled. 2 rxee receive error interrupt enable. default ?low? disabled. 1 ptxe packet transmitted interrupt enable. default ?low? disabled. 0 prxe packet received interrupt enable. default ?low? disabled. 4.3.4 data configuration register ( dcr ) offset 0eh (write) field name description 7 rdcr remote dma alway s completed 6:2 - reserved 1 bos byte order select 0: ms byte placed on ad15:ad8 and ls byte on ad7 - ad0 (80x86). 1: ms byte placed on ad7::ad0 and ls byte on ad15:ad0(68k) 0 wts word transfer select 0 : selects byte - wide dma transfers. 1 : selec ts word - wide dma transfers. 4.3.5 transmit configuration register (tcr) offset 0dh (write) field name description 7 fdu full duplex : this bit indicates the current media mode is full duplex or not. 0 : half duplex 1 : full duplex 6 pd pad di sable 0 : pad will be added when packet length less than 60. 1 : pad will not be added when packet length less tha n 60. 5 rlo retry of late collision 0 : don ? t retransmit packet when late collision happens. 1 : retransmit packet when late collisio n happens. 4:3 - reserved 2:1 lb1,lb0 encoded loop - back control these encoded configuration bits set the type of loop - back that is to be performed. lb1 lb0 mode 0 0 0 normal operation mode 1 0 1 inter nal nic loop - back mode 2 1 0 phycevisor loop - back 0 crc inhibit crc 0 : crc appended by transmitter. 1 : crc inhibited by transmitter.
asix electronics corporation 24 ax88790 l 3 - in - 1 pcmcia fast ethernet controller 4.3.6 transmit status register (tsr) offset 04h (read) field name description 7 owc out of w indow collision 6:4 - reserved 3 abt transmit aborted indicates the ax88790 aborted transmission because of excessive collision. 2 col transmit collided indicates that the transmission collided at least once with another station on the network. 1 - reserved 0 ptx packet transmitted indicates transmission without error. 4.3.7 receive configuration (rcr) offset 0ch (write) field name description 7 int_rg interrupt regeneration 0 : enable interrupt regeneration function in multifunction applic ation. (default) but must set cis relative enable function first, than the function will be open. 1: disable 6 - reserved 5 mon monitor mode 0 : normal operation 1 : monitor mode, the input packet will be checked on node address and crc but not buffe red into memory. 4 pro pro : promiscuous mode enable the receiver to accept all packets with a physical address. 3 am am : accept multicast enable the receiver to accept packets with a multicast address. that multicast address must pass the hashing array . 2 ab ab : accept broadcast enable the receiver to accept broadcast packet. 1 ar ar : accept runt enable the receiver to accept runt packet. 0 sep sep : save error packet enable the receiver to accept and save packets with error. 4.3.8 receive stat us register (rsr) offset 0ch (read) field name description 7 - reserved 6 dis receiver disabled 5 phy multicast address received. 4 mpa missed packet 3 fo fifo overrun 2 fae frame alignment error. 1 cr crc error. 0 prx packet received intact 4 .3.9 inter - frame gap (ifg) offset 16h (read/write) field name description 7 - reserved 6:0 ifg inter - frame gap . default value 15h.
asix electronics corporation 25 ax88790 l 3 - in - 1 pcmcia fast ethernet controller 4.3.10 inter - frame gap segment 1 ( ifgs1 ) offset 12h (read/write) field name description 7 - reserved 6:0 ifg inter - frame gap segment 1 . default value 0ch. 4.3.11 inter - frame gap segment 2 ( ifgs2 ) offset 13h (read/write) field name description 7 - reserved 6:0 ifg inter - frame gap segment 2 . default value 12h. 4.3.12 mii/eeprom management register ( memr ) offset 1 4h (read/write) field name description 7 eeclk eeclk : eeprom clock 6 eeo eeo : (read only) eeprom data out value. that reflects pin - 48 eedo value. 5 eei eei eeprom data in . that output to pin - 49 eedi as eeprom data input value. 4 eecs eecs eep rom chip select 3 mdo mdo mii data out 2 mdi mdi : (read only) mii data in . that reflects pin - 66 mdio value. 1 m dir mii sta mdio signal direction mii read control bit, assert this bit let mdio signal as the input signal. deassert this bit let mdio as output signal. 0 mdc mdc mii clock 4.3.13 test register (tr) offset 15h (write) field name description 7:5 - reserved 4 tf16t test for collision 3 tpe test pin enable 2:0 ifg select test pins output 4.3.14 test register (tr) offset 15h (read) field name description 7:4 - reserved 3 rst_tx b 100base - tx in reset: this signal indicates that 100base - tx logic of internal phy is in reset. 2 rst_10b 10base - t in reset: this signal indicates that 10base - t logic of internal phy is in reset. 1 rst_b reset busy: this signal indicates that internal phy is in reset. 0 autod autonegotiation done: this signal goes high whenever internal phy autonegotiation has completed. it will go low if autonegotiation has to restart.
asix electronics corporation 26 ax88790 l 3 - in - 1 pcmcia fast ethernet controller 4.3.15 general purpose i nput register ( gpi ) offset 17h (read) field name description 7 - reserved 6 gpi2 this register reflects gpi[2] input value. may connect to external phy speed status. 5 gpi1 this register reflects gpi[1] input value. may connect to external phy duplex s tatus. 4 gpi0 this register reflects gpi[0] input value. may connect to external phy link status. 3 - reserved 2 i_spd this register reflects internal phy speed status value. logic one means 100mbps 1 i_dpx this register reflects internal phy duplex st atus value. logic one means full duplex. 0 i_link this register reflects internal phy link status value. logic one means link ok. 4.3.16 gpo and control (gpoc) offset 17h (write) field name description 7:6 - reserved 5 mpset media set by program: th e signal is valid only when mpsel is set to high. when mpset is logic 0, internal phy is selected. when mpset is logic 1, external mii phy is selected. 4 mpsel media priority select : mpsel i_link gpi0 media selected 0 1 0 internal phy 0 1 1 internal phy 0 0 0 external mii phy 0 0 1 internal phy 1 x x depend on mpset bit 3:0 - reserved
asix electronics corporation 27 ax88790 l 3 - in - 1 pcmcia fast ethernet controller 4.4 the embedded phy registers the mii management 16 - bit register set implemented is as follows. and the following sub - s ection will describes each field of the registers. the format for the ?field? descriptions is as follows: the first number is the register number, the second number is the bit position in the register and the name of the instantiated pad is in capital lett ers. the format for the ?type? descriptions is as follows: r = read, w = write, lh = latch high, na = not applicable. address name description default(hex code) 0 mr0 control 3000h 1 mr1 status 7849h 2 mr2 phy identifier 1 0180h 3 mr3 phy identifier 2 bb10h 4 mr4 autonegotiation advertisement 01e1h 5 mr5 autonegotiation link partner ability 0000 6 mr6 autonegotiation expansion 0000 7 mr7 next page transmit 0000 8 - 15 mr8 - 15 (reserved) - 16 mr16 pcs control register 0000 17 mr17 autonegotiat ion (read register a) 0000 18 mr18 autonegotiation (read register b) 0000 19 mr19 analog test register - 20 mr20 user - defined register - 21 mr21 rxer counter 0000 22 - 24 mr22 - 24 analog test registers - 25 - 27 mr25 - 27 analog test (tuner) register s - 28 mr28 device specific 1 - 29 mr29 device specific 2 2080 30 mr30 device specific 3 0000 31 mr31 quick status register - tab ? 18 the embedded phy registers
asix electronics corporation 28 ax88790 l 3 - in - 1 pcmcia fast ethernet controller 4.4.1 mr0 -- control register bit descriptions field type des cription 0.15 (sw_reset) r/w reset. setting this bit to a 1 will reset the phy. all registers will be set to their default state. this bit is self - clearing. the default is 0. 0. 14 (loopback) r/w loopback. when this bit is set to 1, no data transmission w ill take place on the media. any receive data will be ignored. the loopback signal path will contain all circuitry up to, but not including, the pmd. the default value is a 0. 0. 13 (speed100) r/w speed selection. the value of this bit reflects the current speed of operation (1 =100 mbits/s; 0 =10 mbits/s). this bit will only affect operating speed when the autonegotiation enable bit (register 0, bit 12) is disabled (0). this bit is ignored when autonegotiation is enabled (register 0, bit 12). this bit is an ded with the speed_pin signal. 0.12 (nway_ena) r/w autonegotiation enable. the autonegotiation process will be enabled by set - ting this bit to a 1. the default state is a 1. 0.11 (pwrdn) r/w powerdown. the phy may be placed in a low - power state by settin g this bit to a 1, both the 10mbits/s transceiver and the 100mbits/s transceiver will be powered down. while in the powerdown state, the phy will respond to management transactions. the default state is a 0. 0.10 (isolate) r/w isolate. when this bit is se t to a 1, the mii outputs will be brought to the high - impedance state. the default state is a 0. 0.9 (redonway) r/w restart autonegotiation. normally, the autonegotiation process is started at powerup. setting this bit to a 1 may restart the process. the default state is a 0. the nwaydone bit (register 1, bit 5) is reset when this bit goes to a 1. this bit is self - cleared when autonegotiation restarts. 0.8 (full_dup) r/w duplex mode. this bit reflects the mode of operation (1 = full duplex; 0 = half duple x). this bit is ignored when the autonegotiation enable bit (register 0, bit 12) is enabled. the default state is a 0. this bit is ored with the f_dup pin. 0.7 (coltst) r/w collision test. when this bit is set to a 1, the phy will assert the mcol signal i n response to mtx_en. 0.6:0 (reserved) na reserved. all bits will read 0.
asix electronics corporation 29 ax88790 l 3 - in - 1 pcmcia fast ethernet controller 4.4.2 mr1 -- status register bit descriptions field type description 1.15 (t4able) r 100base - t4 ability. this bit will always be a 0. 0: not able. 1: able. 1.14 (txfuldup) r 100base - tx full - duplex ability. this bit will always be a 1. 0: not able. 1: able. 1.13 (txhafdup) r 100base - tx half - duplex ability. this bit will always be a 1. 0: not able. 1: able. 1.12 (enfuldup) r 10base - t full - duplex ability. this bit will always be a 1. 0: not able. 1: able. 1.11 (enhafdup) r 10base - t half - duplex ability. this bit will always be a 1. 0: not able. 1: able. 1.10:7 (reserved) r reserved. all bits will read as a 0. 1.6 (no_pa_ok) r suppress preamble. when this bit is set to a 1, it indicates that the phy accepts management frames with the preamble suppressed. 1.5 (nwaydone) r autonegotiation complete. when this bit is a 1, it indicates the autonegotiation process has been completed. the contents of registers mr4, mr5, mr6, and mr7 are now valid. the default value is a 0. this bit is reset when autonegotiation is started. 1.4 (rem_flt) r remote fault. when this bit is a 1, it indicates a remote fault has been detected. this bit will remain set until cleared by reading the register. the default is a 0. 1.3 (nwayable) r autonegotiation ability. when this bit is a 1, it indicates the ability to perform autonegotiation. the value of this bit is always a 1. 1.2 (lstat_ok) r link status. when this bit is a 1, it indicates a valid link ha s been established. this bit has a latching function: a link failure will cause the bit to clear and stay cleared until it has been read via the management interface. 1.1 (jabber) r jabber detect. this bit will be a 1 whenever a jabber condition is detect ed. it will remain set until it is read, and the jabber condition no longer exists. 1.0 (ext_able) r extended capability. this bit indicates that the phy supports the extended register set (mr2 and beyond). it will always read a 1.
asix electronics corporation 30 ax88790 l 3 - in - 1 pcmcia fast ethernet controller 4.4.3 mr2, mr3 -- identification registers (1 and 2) bit descriptions field type description 2.15:0 (oui[3:18]) r organizationally unique identifier. the third through the twenty - fourth bit of the oui assigned to the phy manufacturer by the ieee are to be placed in bits. 2.15:0 and 3.15:10. this value is programmable. 3.15:10 (oui[19:24]) r organizationally unique identifier. the remaining 6 bits of the oui. the value for bits 24:19 is programmable. 3.9:4 (model[5:0]) r model number. 6 - bit model number of the device. the model number is programmable. 3.3:0 (version[3:0]) r revision number. the value of the present revision number. the version number is programmable. 4.4.4 mr4 ? autonegotiation advertisement registers bit descriptions field type description 4.15 (next _page) r/w next page. setting this bit to a 1 activates the next page function. this will allow the exchange of additional data. data is carried by optional next pages of information. 4.14 (ack) r/w acknowledge. this bit is the acknowledge bit from the li nk code word. 4.13 (rem_fault) r/w remote fault. when set to 1, the phy indicates to the link partner a remote fault condition. 4.12:10 (pause) r/w pause. when set to a 1, it indicates that the phy wishes to exchange flow control information with its lin k partner. 4.9 (100baset4) r/w 100base - t4. this bit should always be set to 0. 4.8 (100baset_fd) r/w 100base - tx full duplex. if written to 1, autonegotiation will advertise that the phy is capable of 100base - tx full - duplex operation. 4.7 (100basetx) r/w 100base - tx. if written to 1, autonegotiation will advertise that the phy is capable of 100base - tx operation. 4.6 (10baset_fd) r/w 10base - t full duplex. if written to 1, autonegotiation will advertise that the phy is capable of 10base - t full - duplex operat ion. 4.5 (10baset) r/w 10base - t. if written to 1, autonegotiation will advertise that the phy is capable of 10base - t operation. 4.4:0 (select) r/w selector field . reset with the value 00001 for ieee 802.3. 4.4.5 mr5 ? autonegotiation link partner abil ity (base page) register bit descriptions field type description 5.15 (lp_next_page) r link partner next page. when this bit is set to 1, it indicates that the link partner wishes to engage in next page exchange. 5.14 (lp_ack) r link partner acknowledge. when this bit is set to 1, it indicates that the link partner has successfully received at least three consecutive and consistent flp bursts. 5.13 (lp_rem_fault) r remote fault. when this bit is set to 1, it indicates that the link partner has a fault. 5.12:5 (lp_tech_ability) r technology ability field. this field contains the technology ability of the link partner. these bits are similar to the bits defined for the mr4 register (see table 16). 5.4:0 (lp_select) r selector field. this field contains th e type of message sent by the link partner. for ieee 802.3 compliant link partners, this field should read 00001.
asix electronics corporation 31 ax88790 l 3 - in - 1 pcmcia fast ethernet controller 4.4.6 mr5 ? autonegotiation link partner (lp) ability register (next page) bit descriptions field type description 5.15 (lp_next_page) r next page . when this bit is set to logic 0, it indicates that this is the last page to be transmitted. logic 1 indicates that additional pages will follow. 5.14 (lp_ack) r acknowledge. when this bit is set to a logic 1, it indicates that the link partner has successfully received its partner?s link code word. 5.13 (lp__mes_page) r message page. this bit is used by the next _page function to differentiate a message page (logic 1) from an unformatted page (logic 0). 5.12 (lp_ack2) r acknowledge 2. this bi t is used by the next_page function to indicate that a device has the ability to comply with the message (logic 1) or not (logic 0). 5.11 (lp_toggle) r toggle . this bit is used by the arbitration function to ensure synchroniza - tion with the link partner d uring next page exchange. logic 0 indicates that the previous value of the transmitted link code word was logic 1. logic 1 indicates that the previous value of the transmitted link code word was logic 0. 5.10:0 (mcf) r message/unformatted code field . with these 11 bits, there are 2048 possible messages. message code field definitions are described in annex 28c of the ieee 802.3u standard. 4.4.7 mr6 ? autonegotiation expansion register bit descriptions field type description 6.15:5 (reserved) r reserved . 6.4 (par_det_fault) r/lh parallel detection fault. when this bit is set to 1, it indicates that a fault has been detected in the parallel detection function. this fault is due to more than one technology detecting concurrent link conditions. this bit ca n only be cleared by reading this register. 6.3 (lp_next_page_ab le) r link partner next page able. when this bit is set to 1, it indicates that the link partner supports the next page function. 6.2 (next_page_able) r next page able. this bit is set to 1, indicating that this device supports the next_page function. 6.1 (page_rec) r/lh page received . when this bit is set to 1, it indicates that a next_page has been received. 6.0 (lp_nway_able) r link partner autonegotiation capable. when this bit is set t o 1, it indicates that the link partner is autonegotiation capable.
asix electronics corporation 32 ax88790 l 3 - in - 1 pcmcia fast ethernet controller 4.4.8 mr7 ? next page transmit register bit descriptions field type description 7.15 (next_page) r/w next page. this bit indicates whether or not this is the last next page to be tra nsmitted. when this bit is 0, it indicates that this is the last page. when this bit is 1, it indicates there is an additional next page. 7.14 (ack) r acknowledge. this bit is the acknowledge bit from the link code word. 7.13 (message) r/w message page. this bit is used to differentiate a message page from an unformatted page. when this bit is 0, it indicates an unformatted page. when this bit is 1, it indicates a formatted page. 7.12 (ack2) r/w acknowledge 2. this bit is used by the next page function t o indicate that a device has the ability to comply with the message. it is set as follows: when this bit is 0, it indicates the device cannot comply with the message. when this bit is 1, it indicates the device will comply with the message. 7.11 (toggle) r toggle. this bit is used by the arbitration function to ensure synchronization with the link partner during next page exchange. this bit will always take the opposite value of the toggle bit in the previously exchanged link code word: if the bit is a lo gic 0, the previous value of the transmitted link code word was a logic 1. if the bit is a 1, the previous value of the transmitted link code word was a 0. the initial value of the toggle bit in the first next page transmitted is the inverse of the value o f bit 11 in the base link code word, and may assume a value of 1 or 0. 7.10:0 (mcf) r/w message/unformatted code field. with these 11 bits, there are 2048 possible messages. message code field definitions are described in annex 28c of the ieee 802.3u stan dard. 4.4.9 mr16 ? pcs control register bit descriptions field type description 16.15 (locked) r locked. locked pin from descrambler block. 16.14 - 12 (unused) r unused. will always be read back as 0. 16.11 - 4 (testbits) r/w generic test bits. these bit s have no effect on the pcs block. they are for external use only. a 0 should be written to these bits. 16.3 (loopback) r/w loopback configure. when this bit is high, the entire loopback is performed in the pcs macro. when this bit is low, only the collis ion pin is disabled in loopback. 16.2 (scan) r/w scan test mode . 16.1 (force loopback) r/w force loopback. force a loopback without forcing idle on the transmit side or disabling the collision pin. 16.0 (speedup counters) r/w speedup counters. reduce li nk monitor counter to 10 us from 620 us. (same as fasttest = 1.)
asix electronics corporation 33 ax88790 l 3 - in - 1 pcmcia fast ethernet controller 4.4.10 mr17 ? autonegotiation register a bit descriptions field type description 17.15 - 13 r reserved. always 0. 17.12 r next page wait. 17.11 r wait link_fail_inhibit_wait_timer (link status check). 17.10 r wait autoneg_wait_timer (link status check). 17.9 r wait break_link_timer (transmit disable). 17.8 r parallel detection fault. 17.7 r autonegotiation enable. 17.6 r flp link good check. 17.5 r complete acknowledge. 17.4 r ack nowledge detect. 17.3 r flp link good. 17.2 r link status check. 17.1 r ability detect. 17.0 r transmit disable. 4.4.11 mr18 ? autonegotiation register b bit descriptions field type description 18.15 r receiving flps . any of flp capture, clock, dat a_0, or data_1 (flp rcv). 18.14 r flp pass (flp rcv). 18.13 r link pulse count (flp rcv). 18.12 r link pulse detect (flp rcv). 18.11 r test pass (nlp rcv). 18.10 r test fail count (nlp rcv). 18.9 r test fail extend (nlp rcv). 18.8 r wait max timer a ck (nlp rcv). 18.7 r detect freeze (nlp rcv). 18.6 r test fail (nlp rcv). 18.5 r transmit count ack (flp xmit). 18.4 r transmit data bit (flp xmit). 18.3 r transmit clock bit (flp xmit). 18.2 r transmit ability (flp xmit). 18.1 r transmit remaining acknowledge (flp xmit). 18.0 r idle (flp xmit). 4.4.12 mr20 ? user defined register bit descriptions field type description 20.[15:0] r/w the data written into this user - defined register appears on the reg20_out[15:0] bus.
asix electronics corporation 34 ax88790 l 3 - in - 1 pcmcia fast ethernet controller 4.4.13 mr21 ? rxer count er register bit descriptions field type description 21.0 w this bit, when 0 puts this register in 16 - bit counter mode. when 1, it puts this register in 8 - bit counter mode. this bit is reset to a 0 and cannot be read. 21.15:0 r when in 16 - bit counter mode , these maintain a count of rxers. it is reset on a read operation. 21.7:0 r when in 8 - bit counter mode, these maintain a count of rxers. it is reset on a read operation 21.11:8 r when in 8 - bit mode, these contain a count of false carrier events (802.3 s ection 27.3.1.5.1). it is reset on a read operaton. 21.15:12 r when in 8 - bit mode, these contain a count of disconnect events (link unstable 6, 802.3 section 27.3.1.5.1). it is reset on a read operation. 4.4.14 mr28 ? device - specific register 1 (status register) bit descriptions field type description 28.15:9 (unused) r unused. read as 0. 28.8 (bad_frm) r/lh bad frame. if this bit is a 1, it indicates a packet has been received without an sfd. this bit is only valid in 10mbits/s mode. this bit is latch ing high and will only clear after it has been read or the device has been reset. 28.7 (code) r/lh code violation. when this bit is a 1, it indicates a manchester code violation has occurred. the error code will be output on the mrxd lines. refer to table 1 for a detailed description of the mrxd pin error codes. this bit is only valid in 10mbits/s mode. this bit is latching high and will only clear after it has been read or the device has been reset. 28.6 (aps) r autopolarity status. when register 30, bit 3 is set and this bit is a 1, it indicates the phy has detected and corrected a polarity reversal on the twisted pair. if the apf_en bit (register 30, bit 3) is set, the reversal will be corrected inside the phy. this bit is not valid in 100mbits/s operat ion. 28.5 (discon) r/lh disconnect. if this bit is a 1, it indicates a disconnect. this bit will latch high until read. this bit is only valid in 100mbits/s mode. 28.4 (unlocked) r/lh unlocked. indicates that the tx scrambler lost lock. this bit will lat ch high until read. this bit is only valid in 100mbits/s mode. 28.3 (rxerr_st) r/lh rx error status. indicates a false carrier. this bit will latch high until read. this bit is only valid in 100mbits/s mode. 28.2 (frc_jam) r/lh force jam. this bit will l atch high until read. this bit is only valid in 100mbits/s mode. 28.1 (lnk100up) r link up 100. this bit, when set to a 1, indicates a 100mbits/s transceiver is up and operational. 28.0 (lnk10up) r link up 10. this bit, when set to a 1, indicates a 10mbi ts/s transceiver is up and operational.
asix electronics corporation 35 ax88790 l 3 - in - 1 pcmcia fast ethernet controller 4.4.15 mr29 ? device - specific register 2 (100mbps control) bit descriptions field type description 29.15 (localrst) r/w management reset. this is the local management reset bit. writing logic 1 to this bit wil l cause the lower 16 registers and registers 28 and 29 to be reset to their default values. this bit is self - clearing. 29.14 (rst1) r/w generic reset 1. this register is used for manufacture test only. 29.13 (rst2) r/w generic reset 2. this register is u sed for manufacture test only. 29.12 (100_off) r/w 100mbits/s transmitter off. when this bit is set to 0, it forces tpi low and tpin - high. this bit defaults to 1. 29.11 (led_blink) r/w led blinking. this register, when 1, enables led blinking. this is o red with led_blink_en. default is 0. 29.10 (crs_sel) r/w carrier sense select. mcrs will be asserted on receive only when this bit is set to a 1. if this bit is set to logic 0, mcrs will by asserted on receive or transmit. this bit is ored with the crs_se l pin. 29.9 (link_err) r/w link error indication. when this bit is a 1, a link error code will be reported on mrxd[3:0] of the phy when mrx_er is asserted on the mii. the specific error codes are listed in the mrxd pin description. if it is 0, it will dis able this function. 29.8 (pkt_err) r/w packet error indication enable. when this bit is a 1, a packet error code, which indicates that the scrambler is not locked, will be reported on mrxd[3:0] of the phy when mrx_er is asserted on the mii. when this bit is 0, it will disable this function. 29.7 (pulse_str) r/w pulse stretching. when this bit is set to 1, the cs, xs, and rs output signals will be stretched between approximately 42 ms - 84 ms. if this bit is 0, it will disable this feature. default state is 0. 29.6 (edb) r/w encoder/decoder bypass. when this bit is set to 1, the 4b/5b - encoder and 5b/4b - decoder function will be disabled. this bit is ored with the edbt pin. 29.5 (sab) r/w symbol aligner bypass. when this bit is set to 1, the aligner function will be disabled. 29.4 (sdb) r/w scrambler/descrambler bypass. when this bit is set to 1, the scrambling/ descrambling functions will be disabled. this bit is ored with the sdbt pin. 29.3 (carin_en) r/w carrier integrity enable. when this bit is set to a 1, carrier integrity is enabled. this bit is ored with the carin_en pin. 29.2 (jam_col) r/w jam enable. when this bit is a 1, it enables jam associated with carrier integrity to be ored with mcolmcrs. 29.1 (fef - en) r/w far - end fault enable . this bit is used to enable the far - end fault detection and transmission capability. this capability may only be used if autonegotiation is disabled. this capability is to be used only with media, which does not support autonegotiation. setting this bit to 1 enables f ar - end fault detection and logic 0 will disable the function. default state is 0. 29.0 (fx) r/w fiber - optic mode. when this bit is a 1, the phy is in fiber - optic mode. this bit is ored with fx_mode.
asix electronics corporation 36 ax88790 l 3 - in - 1 pcmcia fast ethernet controller 4.4.16 mr30 ? device - specific register 3 (10mbps co ntrol) bit descriptions field type description 30.15 (test10tx) r/w when high and 10base - t is powered up, a continuous 10 mhz signal (1111) will be transmitted. this is only meant for testing. default 0. 30.14 (rxpllen) r/w when high, all 10base - t logic will be powered up when the link is up. otherwise, portions of the logic will be powered down when no data is being received to conserve power. default is 0. 30.13 (jab_dis) r/w jabber disable. when this bit is 1, disables the jabber function of the 10bas e - t receive. default is 0. 30.12:7 (unused) r/w unused. read as 0. 30.6 (litf_enh) r/w enhanced link integrity test function. when high, function is enabled. this is ored with the litf_enh input. default is 0. 30.5 (hbt_en) r/w heartbeat enable. when th is bit is a 1, the heartbeat function will be enabled. valid in 10mbits/s mode only. 30.4 (ell_en) r/w extended line length enable. when this bit is a 1, the receive squelch levels are reduced from a nominal 435 mv to 350 mv, allowing reception of signals with a lower amplitude. valid in 10mbits/s mode only. 30.3 (apf_en) r/w autopolarity function disable. when this bit is a 0 and the phy is in 10mbits/s mode, the autopolarity function will determine if the tp link is wired with a polarity reversal. if th ere is a polarity reversal, the phy will assert the aps bit (register 28, bit 6) and correct the polarity reversal. if this bit is a 1 and the device is in 10mbits/s mode, the reversal will not be corrected. 30.2 (reserved) r/w reserved . 30.1 (serial _se l) r/w serial select. when this bit is set to a 1, 10mbits/s serial mode will be selected. when the phy is in 100mbits/s mode, this bit will be ignored. 30.0 (ena_no_lp) r/w no link pulse mode. setting this bit to a 1 will allow 10mbits/s operation with l ink pulses disabled. if the phy is configured for 100mbits/s operation, setting this bit will not affect operation.
asix electronics corporation 37 ax88790 l 3 - in - 1 pcmcia fast ethernet controller 4.4.17 mr31 ? device - specific register 4 (quick status) bit descriptions field type description 31.15 (error) r receiver error. when t his bit is a 1, it indicates that a receive error has been detected. this bit is valid in 100mbits/s only. this bit will remain set until cleared by reading the register. default is a 0. 31.14 (rxerr_st)/(link_st at_change) r false carrier. when bit [31.7] is set to 0 and this bit is a 1, it indicates that the carrier detect state machine has found a false carrier. this bit is valid in 100mbits/s only. this bit will remain set until cleared by reading the register. default is 0. link status change. when bit [31.7] is set to a 1, this bit is redefined to become the link_stat_change bit and goes high whenever there is a change in link status (bit [31.11] changes state) 31.13 (rem_flt) r remote fault. when this bit is a 1, it indicates a remote fault has been detected. this bit will remain set until cleared by reading the register. default is a 0. 31.12 (unlocked)/(jabbe r) r unlocked/jabber. if this bit is set when operating in 100mbits/s mode, it indicates that the tx descrambler has lost lock. if this bit is set when operating in 10mbits/s mode, it indicates a jabber condition has been detected. this bit will remain set until cleared by reading the register. 31.11 (lstat_ok) r link status. when this bit is a 1, it indicates a valid link has been established. this bit has a latching low function: a link failure will cause the bit to clear and stay cleared until it has been read via the management interface. 31.10 (pause) r link partner pause. when this bit is set to a 1, it indicates that the lu3x54ftl wishes to exchange flow control information. 31.9 (speed100) r link speed. when this bit is set to a 1, it indicates that the link has negotiated to 100mbits/s. when this bit is a 0, it indicates that the link is operating at 10mbits/s. 31.8 (full_dup) r duple x mode. when this bit is set to a 1, it indicates that the link has negotiated to full - duplex mode. when this bit is a 0, it indicates that the link has negotiated to half - duplex mode. 31.7 (int_conf) r/w interrupt configuration. when this bit is set to a 0, it defines bit [31.14] to be the rxerr_st bit and the interrupt pin (mask_stat_int) goes high whenever any of bits [31.15:12] go high, or bit [31.11] goes low. when this bit is set high, it redefines bit [31.14] to become the link_stat_change bit, and the interrupt pin (mask_stat_int) goes high only when the link status changes (bit [31.14] goes high). this bit defaults to 0. 31.6 (int_mask) r/w interrupt mask. when set high, no interrupt is generated by this channel under any condition. when set low, interrupts are generated according to bit [31.7]. 31.5:3 (low_auto__state) r lowest autonegotiation state. these 3 bits report the state of the lowest autonegotiation state reached since the last register read, in the priority order defined below: 000: au tonegotiation enable. 001: transmit disable or ability detect. 010: link status check. 011: acknowledge detect. 100: complete acknowledge. 101: flp link good check. 110: next page wait. 111: flp link good. 31.2:0 (hi_auto_state) r highest autonegotiation state. these 3 bits report the state of the highest autonegotiation state reached since the last register read, as defined above for bit [31.5:3].
asix electronics corporation 38 ax88790 l 3 - in - 1 pcmcia fast ethernet controller 5.0 device access functions 5.1 pcmcia interface access functions. 5.1.1 attribute memory access func tion functions. attribute memory read function function mode reg# ce2# ce1# sa0 oe# we# sd[15:8] sd[7:0] standby mode x h h x x x high - z high - z byte access (8 bits) l l h h l l l h l l h h high - z high - z even - byte not valid word access (16 bits) l l l x l h not valid even - byte odd byte only access l l h x l h not valid high - z attribute memory write function function mode reg# ce2# ce1# sa0 oe# we# sd[15:8] sd[7:0] standby mode x h h x x x x x byte access (8 bits) l l h h l l l h h h l l x x even - byt e x word access (16 bits) l l l x h l x even - byte odd byte only access l l h x h l x x 5.1.1 i/o access function functions. i/o read function function mode reg# ce2# ce1# sa0 oe# we# sd[15:8] sd[7:0] standby mode x h h x x x high - z high - z byte acce ss (8 bits) l l h h l l l h l l h h high - z high - z even - byte odd - byte word access (16 bits) l l l l l h odd - byte even - byte i/o inhibit h x x x l h high - z high - z odd byte only access l l h x l h odd - byte high - z i/o write function function mode reg# ce2# ce1# sa0 iord# iowr# sd[15:8] sd[7:0] standby mode x h h x x x x x byte access (8 bits) l l h h l l l h h h l l x x even - byte odd - byte word access (16 bits) l l l l h l odd - byte even - byte i/o inhibit h x x x h l x x odd byte only access l l h x h l o dd - byte x
asix electronics corporation 39 ax88790 l 3 - in - 1 pcmcia fast ethernet controller 5.2 mii station management functions. basic operation the primary function of station management is to transfer control and status information about the phy to a management entity. this function is accomplished by the mdc clock input from m ac entity, which has a maximum frequency of 12.5 mhz (for internal phy only, as to external phy please refer to the relevant specification), along with the mdio signal. the internal phy address is fixed to 10h and the equivalent circuit is shown as below: a specific set of registers and their contents (described in tab - 19) defines the nature of the information transferred across the mdio interface. frames transmitted on the mii management interface will have the frame structure shown in tab - 18. the order of bit transmission is from left to right. note that reading and writing the management register must be completed without interruption. read/write (r/w) pre st op phyad regad ta data idle r 1. . .1 01 10 aaaaa rrrrr z0 dddddddddddddddd z w 1. . .1 01 01 aaaaa rrrrr 10 dddddddddddddddd z tab - 19 mii management frame format field descriptions pre preamble . the phy will accept frames with no preamble. this is indicated by a 1 in register 1, bit 6. st start of frame. the start of frame is indicated by a 01 pattern. op operation code . the operation code for a read transaction is 10. the operation code for a write transaction is a 01. phyadd phy address . the phy address is 5 b its, allowing for 32 unique addresses. the first phy address bit transmitted and received is the msb of the address. a station management entity that is attached to multiple phy entities must have prior knowledge of the appropriate phy address for each ent ity. regad register address. the register address is 5 bits, allowing for 32 unique registers within each phy. the first register address bit transmitted and received is the msb of the address. ta turnaround . the turnaround time is a 2 - bit time spacing b etween the register address field, and the data field of a frame, to avoid drive contention on mdio during a read transaction. during a write to the phy, these bits are driven to 10 by the station. during a read, the mdio is not driven during the first bit time and is driven to a 0 by the phy during the second bit time. data data . the data field is 16 bits. the first bit transmitted and received will be bit 15 of the register being addressed. idle idle condition. the idle condition on mdio is a high - imped ance state. all three state drivers will be disabled and the phy?s pull - up resistor will pull the mdio line to logic 1. tab - 20 mii management frames - field description 0 y (mux) 1 s (internal phy) mdc mdio - out mdio - in if (phy_id==10h) then s=1 else s=0 pin67 mdc pin66 mdio from register offset 14h mdc mdo mdi mdir
asix electronics corporation 40 ax88790 l 3 - in - 1 pcmcia fast ethernet controller 6.0 electrical specification and timings 6.1 absolute max imum ratings description sym min max units operating temperature ta 0 +85 c storage temperature ts - 55 +150 c supply voltage vdd - 0.3 +4.6 v input voltage vin - 0.3 5.5* v output voltage vout - 0.3 vdd+0.5 v lead temperature (soldering 10 seconds ma ximum) tl - 55 +220 c note: stress above those listed under absolute maximum ratings may cause permanent damage to the device. exposure to absolute maximum ratings conditions for extended period, adversely affect device life and reliability. note: * all d igital input signals can sustain 5 volts input voltage except pin - 79 lclk/xtalin 6.2 general operation conditions description sym min tpy max units operating temperature ta 0 25 +75 c supply voltage vdd +3.14 +3.30 +3.46 v 6.3 dc characteristics (vdd =3.3v, vss=0v, ta=0 c to 75 c) description sym min tpy max units low input voltage vil - 0.8 v high input voltage vih 1.9 - v low output voltage vol - 0.4 v high output voltage voh vdd - 0.4 - v input leakage current iil - 1 +1 ua output leakage cu rrent iol - 1 +1 ua description sym min tpy max units power consumption (3.3v) spt3v 87 120 ma note: please reference ? appendix b: power consumption reference data?
asix electronics corporation 41 ax88790 l 3 - in - 1 pcmcia fast ethernet controller 6.4 a.c. timing characteristics 6.4.1 xtal / clock lclk/xtalin tr tf tlow clko tod symbol description min typ. max units t cyc cycle time 40 ns t high clk high time 16 20 24 ns t low clk low time 16 20 24 ns t r/ t f clk slew rate 1 - 4 ns tod lclk/xtalin to clko out delay 10 6.4.2 reset timing lclk reset symbol description min typ. max units trst reset pulse width 100 - - lclk note: some chips may need long power down for successful phy auto negotiation root of cause: the phy inside of ax88 790 has a special request due to the semiconductor?s process. namely, it needs a very long power down for successful auto negotiation for some chips. we made a test in lab and found it would be no problem if the phy's initial time kept for 2 sec for all ch ips . if the power down is less then this number, some of the phy's auto negotiation will not be complete and there will be potential to cause the link fail. if the auto negotiation time is not long enough, uncertain numbers of chip may not work properly. countermeasure: following actions on chip initialization will fix the problem of long auto negotiation. 1. set the phy register mr0 with 0x800h (1000,0000,0000) -- bit 11 of mr0 to '1' (power down mode). 2. wait for 2.5 sec tcyc thigh
asix electronics corporation 42 ax88790 l 3 - in - 1 pcmcia fast ethernet controller 3. set the phy register mr0 with 0x1200h(000 1,0010,0000,0000) -- bit 12,9 of mr0 to '1' (auto negotiation enable and restart auto negotiation)
asix electronics corporation 43 ax88790 l 3 - in - 1 pcmcia fast ethernet controller 6.4.3 attribute memory read timing tcr ta(a) th(a) a[9:0], reg# ta(ce) tv(a) tsu(ce) ce# tsu(a) ta(oe) th(ce) oe# tv(wt - oe) tw(wt) tdis(ce) wait# ten(oe) tv(wt) tdis(oe) d[15:0] data valid symbol descri ption min typ. max units t cr read cycle time 300 - - ns t a(a) address access time - - 120 ns t a(ce) card enable access t ime - - 100 ns t a(oe) output enable access time - - 100 ns t dis(oe) output disable time from oe# 0.5 - - ns t en(oe) output enable time from oe# - - 100 ns t v(a) data valid from addr ess change 0 - - ns t su(a) address setup time 30 - - ns t h(a) address hold time 20 - - ns t su(ce) card enable setup ti me 0 - - ns t h(ce) card enable hold tim e 20 - - ns t v(wt - oe) wait# valid from oe# - - 10 ns t w(wt) wait# pulse width - - 200 ns t v(wt) data setup for wait# released 100 - - ns
asix electronics corporation 44 ax88790 l 3 - in - 1 pcmcia fast ethernet controller 6.4.4 attribute memory write timing tcw a[9:0], reg# tsu(ce - weh) ce# tsu(ce) tsu(a - weh) th(ce) oe# tsu(a) tw(we) trec(we) we# tv(wt - we) tv(wt) tw(wt) th(oe - we) wait# tsu(oe - we) tsu(d - weh) th(d) d[15:0](din) data input establish tdis(we) ten(oe) tdis(oe) te n(we) d[15:0](dout) symbol description min typ. max units t cw write cycle time 250 - - ns t w(we) write pulse width 150 - - ns t su(a) address setup time 30 - - ns t su(a - weh) address setup time f or we# 180 - - ns t su(ce - weh) card ena ble setup time for w e# 180 - - ns t su(d - weh) data setup time for we# 80 - - ns t h(d) data hold time 30 - - ns t rec(we) write recover time 30 - - ns t dis(we) output disable time from we# - - 5 ns t dis(oe) output disable time from oe# - - 5 ns t en(we) output enable time f rom we# 5 - - ns t en(oe) output enable time f rom oe# 5 - - ns t su(oe - we) output enable setup time from oe# 10 - - ns t h(oe - we) output enable hold t ime from oe# 10 - - ns t su(ce) card enable setup ti me 0 - - ns t h(ce) card enable ho ld time 20 - - ns t v(wt - we) wait# valid from we# - - 15 ns t w(wt) wait# pulse width - - 200 ns t v(wt) we# high from wait# released 0 - - ns
asix electronics corporation 45 ax88790 l 3 - in - 1 pcmcia fast ethernet controller 6.4.5 i/o read timing a[9:0] tha tsureg threg reg# tsuce th ce ce# tw iord# tsua tdrinpack inpack# tdfinpack tdriois16 iois16# tdfiois16 td tdr(wt) wait# tdfwt tw(wt) th d[15:0] data valid symbol description min typ. max units t d data del ay after iord# - - 50 ns t h data hold following iord# 0.5 - - ns t w iord# width time 165 - - ns t sua address setup before iord# 70 - - ns t ha address hold before iord# 20 - - ns t suce ce# setup before ior d# 5 - - ns t hce ce# hold before iord # 20 - - ns t sureg reg# setup before io rd# 5 - - ns t hreg reg# hold before ior d# 0 - - ns t dfinpack inpack# delay fallin g from iord# 0 - 10 ns t drinpack inpack# delay rising from iord# - - 10 ns t dfiois16 iois16# delay fallin g from address* - - 10 ns t driois1 6 iois16# delay rising from address* - - 0 ns t dfwt wait# delay falling from iord# - - 5 ns t dr(wt) data delay from wait # rising - - 0 us t w(wt) wait# width time - - 100 ns * note : the address includes reg# and ce1# signal
asix electronics corporation 46 ax88790 l 3 - in - 1 pcmcia fast ethernet controller 6.4.6 i/o write timing a[9:0] tha tsureg threg reg# tsuce th ce ce# tw iowr# tsua tdriois16 iois16# tdfiois16 tdriowr wait# tdfwt tw(wt) th tsu d[15:0] data symbol descri ption min typ. max units t su data setup before io wr# 60 - - ns t h data hold following iowr# 30 - - ns t w iowr# width time 165 - - ns t sua address setup before iowr# 70 - - ns t ha address hold before iowr# 20 - - ns t suce ce# setup before iow r# 5 - - ns t hce ce# hold before iowr # 20 - - ns t sureg reg# setup before io wr# 5 - - ns t hreg reg# hold before iow r# 0 - - ns t dfiois16 iois16# delay fallin g from address* - - 10 ns t driois16 iois16# delay rising from address* - - 0 ns t dfwt wait# delay fall ing from iowr# - - ** ns t w(wt) wait# width time - - ** ns t driowr iowr# high from wait # high 0 - - us *note : the address includes reg# and ce1# signal ** note : there is no wait state while i/o write operation
asix electronics corporation 47 ax88790 l 3 - in - 1 pcmcia fast ethernet controller 6.4.7 mii timing ttclk ttch ttcl txclk ttv tth txd<3:0> txen trclk trch trcl rxclk trs trh rxd<3:0> rxdv trs1 rxer symbol description min typ. max units ttcl k cycle time(100mbps) - 40 - ns ttclk cycle time(10mbps) - 400 - ns ttch high time(100mbps) 14 - 26 ns ttch high time(10mbps) 140 - 260 ns trch low time(100mbps) 14 - 26 ns trch low time(10mbps) 140 - 260 ns ttv clock to data valid - - 20 ns tth dat a output hold time 5 - - ns trclk cycle time(100mbps) - 40 - ns trclk cycle time(10mbps) - 400 - ns trch high time(100mbps) 14 - 26 ns trch high time(10mbps) 140 - 260 ns trcl low time(100mbps) 14 - 26 ns trcl low time(10mbps) 140 - 260 ns trs data setup time 6 - - ns trh data hold time 10 - - ns trs1 rxer data setup time 10 - - ns
asix electronics corporation 48 ax88790 l 3 - in - 1 pcmcia fast ethernet controller 7.0 package information b e d hd e he pin 1 a2 a1 l l1 q a milimeter symbol min. nom max a1 0.05 0.1 0.15 a2 1.35 1.40 1.45 a 1.6 b 0.17 0.22 0.27 d 13.90 14.00 14.10 e 19.90 20.00 20.10 e 0.5 hd 15.60 16.00 16.40 he 21.00 22.00 23.00 l 0.45 0.60 0.75 l1 1.00 q 0 7
asix electronics corporation 49 ax88790 l 3 - in - 1 pcmcia fast ethernet controller appendix a: application note 1 a.1 using crystal 25mhz ax88790 clko25m 25mhz xtalin xtalout 25mh z crystal 33pf 33pf note: the capacitors (33pf) may be various depend on the specification of crystal. while designing, please refer to the suggest circuit provided by crystal supplier. a.2 using oscillator 25mhz ax88790 clko25m 25mhz xtalin xtalout nc 3.3v power osc 25mhz
asix electronics corporation 50 ax88790 l 3 - in - 1 pcmcia fast ethernet controller appendix b: power consumption reference data the following reference data of power consumption are measured base on prime application, that is ax8879 0 + eeprom + 74lv04, at 3.3v/25 c room temperature. note: 74lv04 is used for leds buffer or driver. designer may omit the part and drive led directly by ax88790. item test conditions typical value units 1 power save mode ( power down register bit set to ?1? asserted) 3 ma 2 idel without link 16 ma 3 idel with 10m link 22 ma 4 idel with 100m link 80 ma 5 full traffic with 10mbps at half - duplex mode 37 ? 69 ma 6 full traffic with 10mbps at full - duplex mode 31 ? 57 ma 7 full traffic with 100mbps at ha lf - duplex mode 83 ma 8 full traffic with 100mbps at full - duplex mode 87 ma 9 power save mode ( power down register bit set to ?1? asserted) no led drive 0 ma 10 idel without link, no led drive 12 ma 11 idel with 10m link, no led drive 15 ma 12 idel wi th 100m link, no led drive 74 ma 13 full traffic with 10mbps at half - duplex mode, no led drive 40 ? 68 ma 14 full traffic with 10mbps at full - duplex mode, no led drive 35 ? 60 ma 15 full traffic with 100mbps at half - duplex mode, no led drive 76 ma 16 f ull traffic with 100mbps at full - duplex mode, no led drive 76 ma
asix electronics corporation 51 ax88790 l 3 - in - 1 pcmcia fast ethernet controller errata of ax88790 1. mii station management functions have some differences from previous target specification. description: the target specification is using station management can access both internal phy registers and external phy registers when the phy address is matched as describe in section 5.2. anyway, this version can only access the current selected phy?s registers. how do you know which is the selected media or phy? please refer to section 4.3.16 gpo and control (gpoc) register. solution: the defect will not affect single media application that is using embedded phy. when using mii interface connects to external media (for example homepna) to come out with combo solution. care must be taken, be sure which media is the current selected when you access phy registers.
asix electronics corporation 52 ax88790 l 3 - in - 1 pcmcia fast ethernet controller demonstration circuit (a) : ax88790 + homepna 1m8 phy sa1 sd14 gnd sd6 iowr# sa8 3.3v sd10 reset sa2 *1 r33 : 3.3v card tpye be used. sd8 sa5 ireq# sa3 gnd reg# iois16# r33 1k sa[0..9] gnd ce1# reg# ce2# sd12 iois16# sd4 oe# sd1 gnd c33 0.01u stschg# ce2# sd[0..15] sd9 spkr# wait# reg# gnd stschg# ce1# sd11 ireq# gnd sa9 + c14 4.7uf/16v ireq# + c11 4.7uf/16v vdd c42 0.01u 3.3v c47 0.01u iois16# vdd we# inpack# reset sd0 sd2 wait# gnd u6 lt1117a 1 4 2 3 adj/gnd tab/out out in iord# wait# vdd gnd sd3 sd7 reset we# ce1# sd13 spkr# oe# vdd oe# inpack# sa7 iowr# ce2# ax88790 10base-t/100base-tx & 1m homepna application with ns83851 phyceiver.(reference only) sa0 we# gnd iowr# spkr# iord# sa4 sa6 sd15 790ns2a.sch 1.1 pcmcia interface a4 1 5 monday, july 10, 2000 asix electronics corporation title size document number rev date: sheet of gnd stschg# inpack# sd5 u4 pcmcia pcmcia 168 pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 gnd d3 d4 d5 d6 d7 ce1# a10 oe# a11 a9 a8 a13 a14 we# ireq# vcc vpp1 a16 a15 a12 a7 a6 a5 a4 a3 a2 a1 a0 d0 d1 d2 iois16# gnd gnd cd1# d11 d12 d13 d14 d15 ce2# vs1# iord# iowr# a17 a18 a19 a20 a21 vcc vpp2 a22 a23 a24 a25 vs2# reset wait# inpack# reg# spkr# stschg# d8 d9 d10 cd2# gnd iord# 3.3v
asix electronics corporation 53 ax88790 l 3 - in - 1 pcmcia fast ethernet controller c20 0.01u ce1# rxd1 tpip spkr# ce2# eecs inpack# txen col u1c 74lv04 5 6 txd1 rxer fulled tpon c32 0.01u r17 330 l1 f.b. 1206 c28 0.01u rxd2 spkr# rxdv reset u1f 74lv04 13 12 sd[0..15] zvreg sa8 c23 0.01u iowr# rxd0 rxclk sa2 c31 0.01u c41 0.01u vcc eedo crs gnd c49 0.1u iois16# iord# sd10 xout sa[0..9] tpip c7 0.01u u3 ax88790 1 2 3 4 5 6 7 8 9 10 11 12 15 13 14 16 17 18 19 20 21 22 23 24 25 27 28 26 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 inpack# wait# reset sa0 sa1 sa2 sa3 sa4 sa5 sa6 sa7 sa8 sa9 vdd vss ireq# we# iowr# iord# oe# ce2# ce1# sd15 sd14 sd13 vdd vss sd12 sd11 sd10 sd9 sd8 sd7 vss sd6 sd5 sd4 sd3 sd2 vdd sd1 sd0 vss clko25m bist iddq test2 eedo eedi ppd_set eeck eecs vss vdd vss vssa vdda vdd eeprom_size fast_mode# lnk_led lnk/act_led spddeled act_led full/col_led vss vss test1 mdio mdc vssa vdda tpip tpin vssa vdda rextbs vssa vddm vssm vddpd lclk/xtalin xtalout vsspd vdda rext100 rext10 vssa vsso tpon tpop vsso vsso vddo zvreg vssm vss rxd0 rxd1 rxd2 rxd3 rx_clk crs col rx_dv gpi0/link vdd vss gpi1/dpx tx_clk tx_en txd0 txd1 txd2 txd3 gpi2/spd vdd vss led_op mdcs# mint maudio mrin# mpd_set mpwdn mreset# mrdy iois16# stschg# spkr# vdd vss reg# we# mdc r32 20.1k u1e 74lv04 11 10 tpop reset c29 33p wait# iois16# stschg# sd3 u1d 74lv04 9 8 txd3 r25 20 col ce1# eedi c22 0.01u tpip oe# 3.3v 3.3v sd2 sd13 txd0 3.3v txd3 r37 10k mdc we# iowr# xin ce1# rxd1 3.3v r22 10k r34 10k tpin spdled zvreg txck txd1 sa7 xout *3 pin 58 eeprom size = 0 : 93c46 type 256 byte eeprom is used. pin 58 eeprom size = 1 : 93c56 type 512 byte eeprom is used. (default) pin 116 i_op = 0 : lnk/act & full/col led display be used. pin 116 i_op = 1 : lnk & act led display be used. txd0 zvreg txd3 c37 0.01u spkr# rxd3 txen eedi rxd3 sd0 790ns2a1.sch 1.1 ax88790 a3 2 5 monday, july 10, 2000 asix electronics corporation title size document number rev date: sheet of sa5 c27 33p tpop sd11 sa0 c18 0.01u reg# reset# 3.3v pclk l2 f.b. 1206 sd4 reg# 3.3v l4 f.b. 1206 oe# stschg# txd1 gnd + c3 4.7uf/16v stschg# 3.3v txd2 rxd2 y1 25mhz crystal c10 0.01u sd15 iowr# *3 txen mdio c19 0.01u + c9 4.7uf/16v gnd tpon rxd2 r30 24.9k r31 2.49k ireq# iord# 3.3v gnd c40 0.01u crs sa4 c5 0.01u sa3 eesk iord# col *2 pin 50 ppd_set = 0 : internal phy in normal mode.(default) pin 50 ppd_set = 1 : internal phy in power down mode.(match up cis) sd6 r19 10k rxdv u2 93c56 1 2 3 4 5 6 7 8 cs sk di do gnd nc nc vcc crs rxck + c6 4.7uf/16v inpack# sa9 reset# txd2 wait# oe# sd14 + c4 4.7uf/16v pclk eesk tpin rxck ce2# iois16# rxdv mdio eecs sd7 c21 0.1u r16 330 ireq# lnkled wait# reset# 3.3v r20 10k sd8 reg# rxd0 we# gnd ce2# rxd1 mdc gnd sd1 u1b 74lv04 3 4 rxer *2 sd12 r13 330 inpack# txck 3.3v sa6 u1a 74lv04 1 2 ireq# tpop xin rxd3 pclk txclk tpon tpin eedo sd5 c30 0.01u mdio txd0 sa1 sd9 rxd0 txd2 reset
asix electronics corporation 54 ax88790 l 3 - in - 1 pcmcia fast ethernet controller crs rxdv 3.3v txck txd0 c48 0.1u rxclk txd2 txd3 rxer l3 f.b. 1206 c46 0.1u txclk rxd0 r8 20 col rxd1 pclk hspdled r6 4.7k crs rxer 3.3va1 txd2 3.3v rxck mdio r42 4.7k hcolled ring crs gnd rxck txen txd3 hactled mdio 790ns2a2.sch 1.1 dp83851b a4 3 5 monday, july 10, 2000 asix electronics corporation title size document number rev date: sheet of rxd3 tip txen colled pclk txck r40 4.7k actled mdio c34 0.1u r7 20 hcolled 3.3v hactled rxd3 rxd3 rxd0 r41 330 3.3v reset# u5 dp83851c 36 35 34 33 32 31 23 24 25 26 27 28 37 38 21 22 45 46 19 29 39 5 11 20 7 8 4 17 18 16 15 44 14 42 43 48 30 40 41 47 3 6 10 1 2 9 12 13 txd3 txd2 txd1 txd0/txd tx_en tx_clk rxd3/phyad0 rxd2/cmddis# rxd1/hi_power_en# rxd0/rxd/low_speed_en# rx_dv/gpsi_sel# rx_clk col/mdio_int_en# crs/pin_intrp_en# mdio mdc x1 x2 io_vdd1 io_vdd2 core_vdd ana_vdd2 ana_vdd3 io_gnd1 tip ring rbias led_col/phyad2 led_act/phyad1 led_speed/phyad3 led_power/phyad4 reset# reserved reserved reserved ana_vdd1 io_gnd2 core_gnd core_sub(0v) ana_gnd1 ana_gnd2 ana_gnd3 ana_gnd4 sub_gnd1 sub_gnd2 sub_gnd3 reserved reserved reset# r5 2k gnd pwrled gnd hspdled colled txen rxd2 ring rxd1 rxd0 r45 9.31k 1% mdc reset# tip 3.3v + c15 4.7uf/16v actled ring 3.3v gnd hcolled rxd2 c45 0.1u spdled c38 0.1u r43 330 c43 0.1u rxd1 r4 4.7k c39 0.1u txd1 spdled rxdv col r39 330 rxdv 3.3va2 txd1 hactled mdc spdled r44 4.7k 3.3v c35 0.1u pclk c36 0.1u pwrled 3.3v hspdled c44 0.1u txd2 txd0 mdc gnd col colled set phy address to 00001. actled gnd tip txd0 txd1 l5 f.b. 1206 rxd2 txd3 rxd3
asix electronics corporation 55 ax88790 l 3 - in - 1 pcmcia fast ethernet controller tpop tpon lring tx+ hspdled r27 75 t1 16st0009p 6 7 8 1 2 3 11 10 9 16 15 14 ct td+ td- rd+ rd- ct ct tx+ tx- rx+ rx- ct hcolled tx- rx- spdled lring fulled t2 lhr002 4 6 1 2 11 9 14 13 tut+ tut- z+ z- tip+ ring- c+ c- c13 p0800sa d0-214aa 3.3v r10 75 *4 1ct : 1ct chassis c16 0.01u c24 0.01u c26 0.1u tip hcolled hspdled tpin + c2 10uf/16v r14 49.9 tx- hactled tip r2 49.9 gnd r12 0 tpip r26 75 ring ltip zvreg hactled ring spdled r3 49.9 tpin 3.3v tpop tpip gnd ring rx+ tpop tpon c1 0.01u/2kv tip rx+ zvreg lnkled ltip zvreg hactled tpip c12 0.01u/2kv 3.3v lnkled r28 49.9 r9 1m *5 receive 1ct : 1ct transmit 1ct : 1ct tpon tpin fulled r15 49.9 gnd hspdled tx+ rx- j5 pcmcia15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r11 75 lnkled spdled r29 49.9 c17 0.1u c8 0.1u c25 0.001u 790ns2a3.sch 1.1 16st009p & lhr002 a4 4 5 monday, july 10, 2000 asix electronics corporation title size document number rev date: sheet of hcolled fulled
asix electronics corporation 56 ax88790 l 3 - in - 1 pcmcia fast ethernet controller rx- on : full dpx blink : activity 790ns2a4.sch 1.1 rj45 / rj11 connect & led a4 5 5 monday, july 10, 2000 asix electronics corporation title size document number rev date: sheet of hspdled hcolled j2 rj45n 1 2 3 6 4 5 7 8 rx+ lring spdled d6 led d2 led r45 r78 tx+ hcolled hspdled d4 led lnkled on : link ok off : link fail rx+ tx- on : 100m off : 10m hactled on : link blink : activity gnd lnkled blink : collision j3 con8 1 2 3 4 5 6 7 8 gnd fulled r78 hactled tx- tx+ ltip ltip lring d5 led r45 j1 con8 1 2 3 4 5 6 7 8 j4 rj11-s 1 2 3 4 5 6 nc a1 tip ring a2 nc d1 led fulled d3 led on : 1m off : 0.7m rx- spdled
asix electronics corporation 57 ax88790 l 3 - in - 1 pcmcia fast ethernet controller demonstration circuit (b) : ax88790 only iois16# gnd iois16# 3.3v sa[0..9] wait# + c11 4.7uf/16v sa4 we# ireq# vdd we# u4 pcmcia pcmcia 168 pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 gnd d3 d4 d5 d6 d7 ce1# a10 oe# a11 a9 a8 a13 a14 we# ireq# vcc vpp1 a16 a15 a12 a7 a6 a5 a4 a3 a2 a1 a0 d0 d1 d2 iois16# gnd gnd cd1# d11 d12 d13 d14 d15 ce2# vs1# iord# iowr# a17 a18 a19 a20 a21 vcc vpp2 a22 a23 a24 a25 vs2# reset wait# inpack# reg# spkr# stschg# d8 d9 d10 cd2# gnd reset u6 lt1117a 1 4 2 3 adj/gnd tab/out out in iowr# iord# sd12 oe# gnd 790tx1a.sch 1.1 pcmcia interface a4 1 4 monday, july 10, 2000 asix electronics corporation title size document number rev date: sheet of ce1# vdd sa9 c47 0.01u sd2 iowr# gnd ce1# sd7 we# inpack# sd4 ce2# sa6 gnd oe# sa5 iois16# sd[0..15] 3.3v ce2# ce2# inpack# sa7 iord# iord# gnd reg# sd3 reset sd5 sa3 gnd stschg# sd8 gnd sa2 sd10 + c14 4.7uf/16v spkr# sa8 spkr# reg# inpack# vdd ireq# reset sa1 sd14 stschg# sd11 *1 r33 : 3.3v card tpye be used. vdd ax88790 10base-t/100base-tx application. (reference only) sd13 oe# gnd r33 1k gnd gnd sd6 spkr# ce1# c33 0.01u wait# iowr# sd15 stschg# c42 0.01u sd1 3.3v sa0 reg# sd0 ireq# sd9 wait#
asix electronics corporation 58 ax88790 l 3 - in - 1 pcmcia fast ethernet controller sa0 u1e 74lv04 11 10 u2 93c56 1 2 3 4 5 6 7 8 cs sk di do gnd nc nc vcc + c9 4.7uf/16v c23 0.01u sd0 c5 0.01u c41 0.01u tpon gnd ce1# tpop wait# eesk c21 0.1u 3.3v tpop sd14 l4 f.b. 1206 c27 20p r19 10k tpip u3 ax88790 1 2 3 4 5 6 7 8 9 10 11 12 15 13 14 16 17 18 19 20 21 22 23 24 25 27 28 26 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 inpack# wait# reset sa0 sa1 sa2 sa3 sa4 sa5 sa6 sa7 sa8 sa9 vdd vss ireq# we# iowr# iord# oe# ce2# ce1# sd15 sd14 sd13 vdd vss sd12 sd11 sd10 sd9 sd8 sd7 vss sd6 sd5 sd4 sd3 sd2 vdd sd1 sd0 vss clko25m bist iddq test2 eedo eedi ppd_set eeck eecs vss vdd vss vssa vdda vdd eeprom_size fast_mode# lnk_led lnk/act_led spddeled act_led full/col_led vss vss test1 mdio mdc vssa vdda tpip tpin vssa vdda rextbs vssa vddm vssm vddpd lclk/xtalin xtalout vsspd vdda rext100 rext10 vssa vsso tpon tpop vsso vsso vddo zvreg vssm vss rxd0 rxd1 rxd2 rxd3 rx_clk crs col rx_dv gpi0/link vdd vss gpi1/dpx tx_clk tx_en txd0 txd1 txd2 txd3 gpi2/spd vdd vss led_op mdcs# mint maudio mrin# mpd_set mpwdn mreset# mrdy iois16# stschg# spkr# vdd vss reg# r38 330 c40 0.01u stschg# tpip oe# stschg# r30 24.9k oe# sa9 r39 330 tpin c7 0.01u u1f 74lv04 13 12 reg# sd11 c37 0.01u *3 led low activity : r40,r39,r38 be used. led high activity : r17,r13,r16,u1 be used. eesk 3.3v gnd r22 10k we# we# zvreg spkr# c28 0.01u c18 0.01u tpin spdled 3.3v *3 eecs inpack# u1c 74lv04 5 6 tpop tpon reset l1 f.b. iois16# sa4 c22 0.01u inpack# reset tpon + c3 10uf/16v 1206 eedi eedo sd7 c32 0.01u r20 10k r13 330 sa2 iois16# sd5 u1d 74lv04 9 8 reset gnd tpin sd4 3.3v 3.3v reg# zvreg u1a 74lv04 1 2 iois16# ce2# *2 pin 50 ppd_set = 0 : internal phy in normal mode.(default) pin 50 ppd_set = 1 : internal phy in power down mode.(match up cis) iowr# 790tx1a1.sch 1.2 ax88790 a3 2 4 thursday, august 31, 2000 asix electronics corporation title size document number rev date: sheet of reg# u1b 74lv04 3 4 c48 0.1u oe# r31 2.49k spkr# sa[0..9] spkr# sd1 xout eedo ce1# sd9 tpip gnd r17 330 zvreg sd8 sa3 iowr# reset# ce2# sa8 sa1 ce2# lnkled ireq# *4 pin 58 eeprom size = 0 : 93c46 type 256 byte eeprom is used. pin 58 eeprom size = 1 : 93c56 type 512 byte eeprom is used. (default) pin 116 i_op = 0 : lnk/act & full/col led display be used. pin 116 i_op = 1 : lnk & act led display be used. *4 xout 3.3v iord# 3.3v r32 20.1k l2 f.b. 1206 3.3v r40 330 iord# + c6 4.7uf/16v sd[0..15] we# ireq# eecs xin r37 10k sd6 xin 3.3v c19 0.01u sd15 sd3 sa6 sd10 ireq# ce1# sa5 stschg# gnd wait# 3.3v c29 20p c10 0.01u y1 25mhz crystal sd2 wait# sd12 iowr# sd13 r1 2m iord# eedi fulled *2 inpack# c30 0.01u c31 0.01u r16 330 sa7
asix electronics corporation 59 ax88790 l 3 - in - 1 pcmcia fast ethernet controller rx+ zvreg tx+ zvreg tpop lnkled 3.3v_out lnkled chassis 790tx1a2.sch 1.1 16st009p a4 3 4 monday, july 10, 2000 asix electronics corporation title size document number rev date: sheet of *5 r41 : led low activity be used. tpin zvreg r42 75 r15 49.9 *6 receive 1ct : 1ct transmit 1ct : 1ct r41 0 tpon fulled c17 0.1u fulled spdled gnd c25 0.001u tpin rx- c1 0.01u/2kv j5 pcmcia15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 spdled 3.3v r43 75 tpin r10 75 fulled tpon gnd tpip lnkled + c2 10uf/16v tx- r28 49.9 tpip tx- tpop tx+ 3.3v_out tpop c24 0.01u rx+ rx- r14 49.9 r29 49.9 c50 0.01u r11 75 gnd spdled t1 16st0009p 6 7 8 1 2 3 11 10 9 16 15 14 ct td+ td- rd+ rd- ct ct tx+ tx- rx+ rx- ct tpip tpon c26 0.1u c16 0.01u
asix electronics corporation 60 ax88790 l 3 - in - 1 pcmcia fast ethernet controller on : link ok off : link fail tx- 790tx1a3.sch 1.1 rj45 connect & led a4 4 4 monday, july 10, 2000 asix electronics corporation title size document number rev date: sheet of tx+ gnd rx- on : 100m off : 10m lnkled d6 led spdled fulled rx+ j2 rj45n 1 2 3 6 4 5 7 8 j1 con8 1 2 3 4 5 6 7 8 lnkled d2 led r78 d5 led rx+ rx- on : full dpx blink : activity r78 r45 tx- tx+ j3 con8 1 2 3 4 5 6 7 8 spdled gnd r45 fulled

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